Abstract: An apparatus may include an input pin\ and timing control circuitry coupled to the input pin. The timing control circuitry selectively executes one or more timing control functions based on a set of one or more hardware components coupled to the input pin. The set of one or more hardware components are disposed external to the apparatus. A configuration of the set of one or more hardware components determines which of one or more of the multiple timing control functions are enabled.

Abstract: A gate charge profiler for a power transistor may include a voltage comparator unit and a timer unit. An input signal may control a gate drive current input to a gate of the power transistor to control conduction between a drain and a source of the power transistor. The voltage comparator unit may be configured to compare an input voltage and a threshold voltage, and to output a comparison signal. The input voltage may be a drain-source voltage across the drain and the source of the power transistor or a gate-source voltage across the gate and the source of the power transistor. The timer unit may be configured to output a time value based on input of a transition of the input signal and input of the comparison signal.

Abstract: A gate charge profiler for a power transistor may include a voltage comparator unit and a timer unit. An input signal may control a gate drive current input to a gate of the power transistor to control conduction between a drain and a source of the power transistor. The voltage comparator unit may be configured to compare an input voltage and a threshold voltage, and to output a comparison signal. The input voltage may be a drain-source voltage across the drain and the source of the power transistor or a gate-source voltage across the gate and the source of the power transistor. The timer unit may be configured to output a time value based on input of a transition of the input signal and input of the comparison signal.

Abstract: A first partial power converter implementation receives and converts an input voltage into multiple auxiliary voltages including a first auxiliary voltage and a second auxiliary voltage. The first partial power converter produces a first output voltage as a first summation of the first auxiliary voltage and the input voltage; the first partial power converter produces a second output voltage as a second summation of the second auxiliary voltage and the input voltage. A second partial power converter implementation as discussed herein receives a first auxiliary input voltage referenced with respect to an output voltage of the power converter. The second partial power converter also receives a second auxiliary input voltage referenced with respect to the output voltage. The second partial power converter converts the first auxiliary input voltage and the second auxiliary input voltage into the output voltage to power a load.

Abstract: A multi-level converter comprises one or more flying capacitors configured to operate at balanced voltages. The multi-level converter comprises a plurality of switching groups comprising pairs of switches operable to transfer energy to and from an inductor and the one or more flying capacitors for inverting an input voltage to an inverted output voltage. The multi-level converter comprises the inductor configured to operate according to an inductor frequency greater than a switching frequency used to control the plurality of switching groups.

Abstract: Circuits, methods, and systems are provided for setting a current level to be used by a current-mode gate driver. The current level may be used to source, sink, or both source and sink current to/from the gate terminal of a power device. The current level is based upon a current or voltage level input from an analog current-setting terminal. This input current or voltage level may take a value from a continuous range of current or voltage values.

Abstract: Circuits, methods, and systems are provided for setting a current level to be used by a current-mode gate driver. The current level may be used to source, sink, or both source and sink current to/from the gate terminal of a power device. The current level is based upon a current or voltage level input from an analog current-setting terminal. This input current or voltage level may take a value from a continuous range of current or voltage values.

Abstract: A power converter circuit includes a transformer. The transformer includes a primary winding and a secondary winding. A primary circuit is coupled to the primary winding. A secondary circuit is coupled to the secondary winding. The primary circuit and the secondary circuit are referenced to different ground voltage potentials that may vary with respect to each other. During operation, the primary circuit controls input of energy to the primary winding of the transformer. The secondary circuit receives the energy through the secondary winding and uses it to produce an output voltage to power a load. The secondary circuit receives and/or generates state information at one of multiple different levels. The secondary circuit controls a flow of current through the secondary winding to convey the state information as feedback to the primary circuit. The primary circuit analyzes a voltage at a node of the primary winding to receive the feedback.

Abstract: In some examples, a device includes a gate driver circuit and a control circuit configured to generate a first signal and a second signal, a duty cycle of the first signal encoding an amplitude of an electrical current having a sinusoidal shape, and a duty cycle of the second signal encoding a phase angle of the electrical current. The control circuit is configured to deliver the first and second signals to the gate driver circuit, which is configured to determine a duty cycle of a driver signal as a function of the first signal and of the second signal. The gate driver circuit is also configured to deliver the driver signal to a switch to cause the electrical current having the sinusoidal shape to be delivered to an electrical load.

Abstract: A voltage regulator controller includes a first pin for receiving aggregate temperature information from a plurality of power stages, a plurality of second pins each for receiving phase current information from one of the power stages, control circuitry for controlling the power stages, detection circuitry for detecting signal levels at the first and second pins, and fault analysis circuitry for identifying the type of reported fault and the power stage that reported the fault based on the detected signal levels at the first and second pins and state information accessible by the controller. Aggregate temperature information is reported at the first pin in a first nominal range, and phase current information is reported at each of the second pins in a second nominal range. Each reported fault type has a unique fault signature at the first and second pins, which is outside at least one of the nominal ranges.

Abstract: Circuits, methods, and systems are provided for setting a current level to be used by a current-mode gate driver. The current level may be used to source, sink, or both source and sink current to/from the gate terminal of a power device. The current level is based upon a current or voltage level input from an analog current-setting terminal. This input current or voltage level may take a value from a continuous range of current or voltage values.

Abstract: Circuits, methods, and systems are provided for setting a current level to be used by a current-mode gate driver. The current level may be used to source, sink, or both source and sink current to/from the gate terminal of a power device. The current level is based upon a current or voltage level input from an analog current-setting terminal. This input current or voltage level may take a value from a continuous range of current or voltage values.

Abstract: In some examples, a device includes a gate driver circuit and a control circuit configured to generate a first signal and a second signal, a duty cycle of the first signal encoding an amplitude of an electrical current having a sinusoidal shape, and a duty cycle of the second signal encoding a phase angle of the electrical current. The control circuit is configured to deliver the first and second signals to the gate driver circuit, which is configured to determine a duty cycle of a driver signal as a function of the first signal and of the second signal. The gate driver circuit is also configured to deliver the driver signal to a switch to cause the electrical current having the sinusoidal shape to be delivered to an electrical load.

Abstract: A semiconductor device includes a main transistor and a sense transistor. The main transistor is disposed in a semiconductor body and includes a plurality of sections which are individually controllable via separate gate electrodes disposed above the semiconductor body. The sense transistor is disposed in the same semiconductor body as the main transistor and has the same number of individually controllable sections as the main transistor. Each individually controllable section of the sense transistor is configured to mirror current flowing through one of the individually controllable sections of the main transistor and is connected to the same gate electrode as that individually controllable section of the main transistor. An electronic circuit that includes the semiconductor device and a current sense circuit that outputs a current sense signal representing the current mirrored by the sense transistor is also provided.

Abstract: In accordance with an embodiment, switch driver includes a first switch driver configured to be coupled to a control node of a first switch, a second driver configured to be coupled to a control node of a second switch, and a first terminal and a second terminal configured to be couple to a boot capacitor. The first terminal is coupled between a boot input of the first switch driver and the second terminal is configured to be coupled to outputs of the first switch and the second switch. The switch driver further includes a voltage measurement circuit coupled to the first terminal and the second terminal, and a control circuit configured to activate the second switch driver when the voltage measurement circuit indicates that a voltage across boot capacitor is below a first threshold.

Abstract: A voltage regulator controller includes a first pin for receiving aggregate temperature information from a plurality of power stages, a plurality of second pins each for receiving phase current information from one of the power stages, control circuitry for controlling the power stages, detection circuitry for detecting signal levels at the first and second pins, and fault analysis circuitry for identifying the type of reported fault and the power stage that reported the fault based on the detected signal levels at the first and second pins and state information accessible by the controller. Aggregate temperature information is reported at the first pin in a first nominal range, and phase current information is reported at each of the second pins in a second nominal range. Each reported fault type has a unique fault signature at the first and second pins, which is outside at least one of the nominal ranges.

Abstract: A voltage regulator controller includes a first pin for receiving aggregate temperature information from a plurality of power stages, a plurality of second pins each for receiving phase current information from one of the power stages, control circuitry for controlling the power stages, detection circuitry for detecting signal levels at the first and second pins, and fault analysis circuitry for identifying the type of reported fault and the power stage that reported the fault based on the detected signal levels at the first and second pins and state information accessible by the controller. Aggregate temperature information is reported at the first pin in a first nominal range, and phase current information is reported at each of the second pins in a second nominal range. Each reported fault type has a unique fault signature at the first and second pins, which is outside at least one of the nominal ranges.

Abstract: A voltage regulator controller includes a first pin for receiving aggregate temperature information from a plurality of power stages, a plurality of second pins each for receiving phase current information from one of the power stages, control circuitry for controlling the power stages, detection circuitry for detecting signal levels at the first and second pins, and fault analysis circuitry for identifying the type of reported fault and the power stage that reported the fault based on the detected signal levels at the first and second pins and state information accessible by the controller. Aggregate temperature information is reported at the first pin in a first nominal range, and phase current information is reported at each of the second pins in a second nominal range. Each reported fault type has a unique fault signature at the first and second pins, which is outside at least one of the nominal ranges.

Abstract: A power converter circuit includes a transformer. The transformer includes a primary winding and a secondary winding. The power converter circuit uses energy conveyed from the primary winding of the transformer through the secondary winding of the transformer to produce an output voltage to power a load. Control circuitry of the power converter circuit initiates conveying a portion of the received energy through the secondary winding back through the primary winding to control a magnitude of the output voltage. For example, if the magnitude of the output voltage is above a desired setpoint value, such as due to a transient load condition or change in the setpoint of the output voltage, the control circuitry reduces the magnitude of the output voltage by conveying excess energy from an output capacitor (that stores the output voltage) through the secondary winding to the primary winding.

Abstract: In some examples, a device includes level-shifter circuitry and biasing circuitry including at least four diodes, wherein each diode of the at least four diodes is electrically connected in series. The biasing circuitry further includes push-pull circuitry electrically connected to at least two diodes of the at least four diodes and configured to generate an intermediate voltage signal. The biasing circuitry is configured to deliver a high-side biasing signal to the level-shifter circuitry based on the intermediate voltage signal and a high-side voltage signal from the at least four diodes. The biasing circuitry is further configured to deliver a low-side biasing signal to the level-shifter circuitry based on the intermediate voltage signal and a low-side voltage signal from the at least four diodes.