Abstract: A polar modulator has a low AM-AM and AM-PM distortion comprises a phase locked loop. The phase locked loop is designed for outputting a high-frequency signal with a frequency derived from a phase modulation signal at an actuating input of the phase locked loop. A filter device, for suppressing a DC signal component, is coupled to an output of the phase locked loop. Furthermore, provision is made of a controllable voltage source with a control input suitable for feeding in an amplitude modulation signal. A push-pull amplifier is connected by an input to the filter device. It comprises two feedback amplifier transistors connected in series, which are connected to a voltage output of the controllable voltage source for supply purposes. Control terminals of the amplifier transistors are connected to the input and, via a load, to an output of the push-pull amplifier.

Abstract: An arrangement for testing a plurality of capacitances in a capacitance array of an integrated circuit includes a power supply and a means for cyclically charging and discharging at least one of the capacitances. In this arrangement, the cycle frequency is dependent on the value of the capacitance. The cycle frequency or a quantity characteristic associated therewith is measured by a means to ascertain a value of the capacitance under test.

Abstract: An assembly includes a substrate, a chip mounted on the substrate, a voltage controlled oscillator circuit including an inductor and further circuit elements. The inductor is mounted on or in the substrate, and the further circuit elements are mounted on or in the chip. An assembly is disclosed that includes a substrate including a first metallization plane and a second metallization plane, a chip mounted on the substrate, and an inductor mounted on or in the substrate. The inductor includes a first inductor portion in the first metallization plane and a second inductor portion in the second metallization plane. An assembly is also disclosed including a substrate, a chip mounted onto the substrate, and a transformer formed at least in part on or in the substrate.

Abstract: A sigma-delta modulator arrangement is disclosed that has a mechanism for breaking down a data word of the input signal into subwords with a different significance. The disclosed sigma-delta modulator arrangement also has a plurality of sigma-delta modulators whose inputs are assigned to respective subwords of the input signal.

Abstract: A VCO circuit (20) has a coil (21) and, in parallel therewith, a constant capacitance (24) and adjustable capacitance elements (22, 23). A first capacitance element (22) is formed by one or more varactors whose capacitance can be adjusted by an analogue adjusting voltage (Vtune), while a second capacitance element (23) is formed by an arrangement comprising a plurality of capacitors which can be actuated by a digital bit word VCWD[N:1]. Digital calibration for the VCO (20) is performed by determining whether the present adjusting voltage is within a particular voltage range and, if this is not the case, the digital bit word being incremented or decremented by a bit value.

Abstract: A polar modulator contains a phase locked loop which is designed to emit a radio-frequency signal at one frequency to one output, with the frequency being derived from the reference signal and from a phase modulation signal at a control input of the phase locked loop. The modulator additionally has a second signal input for supplying an amplitude modulation signal. The second signal input is connected to a control input of a pulse width modulator, one of whose signal inputs is coupled to the output of the phase locked loop. The pulse width modulator is designed to vary the duty ratio of a signal which is applied to the signal input, with this variation being adjustable via a regulation signal at the control input. A filter can be connected downstream from the output of the pulse width modulator and suppresses higher harmonic components in a signal which can be tapped off at the output of the pulse width modulator.

Abstract: The invention provides a phase locked loop having a modulator which is based on a ?? fractional N phase locked loop. In the forward path of the PLL, the output of the oscillator has an additional frequency divider which provides the output frequency of the PLL in a plurality of different phases. A multiplexer which is connected upstream of the multimodulus divider in the PLL's feedback path and which is actuated by the ?? modulator, like the divider, selects the respective desired phase. This allows the minimum step size of the division factors to be reduced to values of less than 1 relative to the output frequency, which significantly reduces the quantization noise. The PLL bandwidth may therefore advantageously be the same size as the modulation bandwidth.

Abstract: A sigma-delta converter has a signal input for receiving a data word. A clock signal input is designed to supply a clock signal. The sigma-delta converter includes a first clocked-operation accumulator stage whose input side is connected to the signal input, and at least one second clocked-operation accumulator stage connected in series with the first accumulator stage, with its input side coupled to an accumulator output of the first accumulator stage. The sigma-delta converter is configured to process the data word upon each clock signal only in one accumulator stage in the first and the at least one second accumulator stage, and output the processed data word at the accumulator output of the one accumulator stage. As a result, a time-critical response during signal processing is limited just to the accumulator stage which is currently processing the data word.

Abstract: The invention is directed to a phase locked loop with a ?? modulator. A multimodulus divider in the feedback path of the PLL is actuated by the ?? modulator. The latter has a design which can be described by a complex transfer function H(s) in the Laplace plane, said transfer function having a complex-conjugate pair of pole points. The arrangement allows a significant reduction in the noise in critical frequency domains and hence allows adherence to transmission masks based on radio specification even when the PLL bandwidth is as large as the modulation bandwidth.

Abstract: A traveling wave amplifier comprises a first normally off MOS transistor having a drain, source and gate terminal. The drain terminal is connected to a node of a drain line, which is connected to a first supply voltage potential via a connecting resistor. The gate terminal is connected to a node of a gate line, onto which an input signal is coupled. The source terminal is coupled to a second supply voltage potential via a first resistor. The traveling wave amplifier also comprises at least one second normally off MOS transistor. In addition, the traveling wave amplifier further comprises a normally off bias MOS transistor. The normally off bias MOS transistor forms a current mirror with at least one of the second normally off MOS transistors. An output signal of the traveling wave amplifier is tapped off on the drain line.

Abstract: A PLL circuit is tuned to a first frequency by using a first digital modulation signal and subsequently tuned to a second frequency by using a second digital modulation signal. A differential signal, that is a function of the change in voltage of a VCO control signal generated by the modulation signals, is compared with a comparison signal, that is characteristic of the analog modulation amplitude. Based on the comparison the analog modulation amplitude is changed to minimize or substantially eliminate a deviation between the signals.

Abstract: A circuit arrangement for detecting a usable frequency channel includes first and second devices for performing frequency conversion. The first and second frequency conversion devices have respective local oscillator inputs to which respective local oscillator signals are applied. The local oscillator signals are at a common frequency and have a phase difference of precisely 90°. A complex polyphase filter has first and second filter inputs connected to respective outputs of the first and second frequency conversion devices. A detection arrangement is connected to outputs of the complex polyphase filter in order to detect a signal level. A further arrangement can vary the phase angle of a signal output from at least one of the frequency conversion devices.

Abstract: The invention is directed to a phase locked loop with a ?? modulator. A multimodulus divider in the feedback path of the PLL is actuated by the ?? modulator. The latter has a design which can be described by a complex transfer function H(s) in the Laplace plane, said transfer function having a complex-conjugate pair of pole points. The arrangement allows a significant reduction in the noise in critical frequency domains and hence allows adherence to transmission masks based on radio specification even when the PLL bandwidth is as large as the modulation bandwidth.

Abstract: The phase locked loop according to the invention has an adjustable charge pump (2) which is intended to generate a control voltage (UVCO). A voltage-controlled oscillator (4) and an evaluation unit (14) are connected downstream of said charge pump. In this case, the evaluation unit (14) is designed in such a manner that it can be used to generate a correction signal (Iref) using the control voltage (UVCO) and a nominal gradient ({circumflex over (K)} vco) of the voltage-controlled oscillator (4) and to apply said signal to the evaluation output. The latter is, in turn, connected to an input of the charge pump (2).

Abstract: Amplifier for an ultra-wideband (UWB) signal receiver having a signal input (15) for receiving an ultra-wideband signal which is sent by a transmitter (1) and which is transmitted in a sequence of transmission channels (Ki) (which each have a particular frequency bandwidth) which has been agreed between the transmitter (1) and the receiver (4); a transistor (18) whose control connection is connected to the signal input (15); a resonant circuit (26, 30, 31) which is connected to the transistor (18) and whose resonant frequency can be set for the purpose of selecting the transmission channel (Ki) in line with the agreed sequence of transmission channels; and having a signal output (29) for outputting the amplified ultra-wideband signal, the signal output being tapped off between the transistor (18) and the resonant circuit.

Abstract: A current source circuit for generating a low-noise current has a current mirror circuit with a first and a second transistor. The current mirror circuit contains a capacitor connected between a source connection and a gate connection of the second transistor. The current mirror circuit likewise contains a switching element disposed between a drain connection of the first transistor and the gate connection of the second transistor. The switching element may be controlled as a function of an operating state of the current source circuit.

Abstract: Circuit arrangement for a wideband mixer (1, 101, 201) with a multiplicative mixing stage (2) which exhibits a carrier frequency input (3, 4) for coupling in a differential carrier frequency signal (LOP, LON), a mixing stage input (5, 6) for coupling in a predistorted differential input signal (LFPD, LFND), and an output (9, 10) for coupling out a differential output signal (OUTP, OUTN) which is generated from the differential carrier frequency signal (LOP, LON) and the predistorted differential input signal (LFPD, LFND) by multiplicative mixing, the predistorted differential input signal (LFPD, LFND) being generated from a differential input signal (LFP, LFN) by means of a quadratic predistortion and a linear predistortion.

Abstract: Frequency pattern generator (1, 101, 201) for generating frequency pulses, said generator having a first local oscillator unit (2-1, 121, 221) for generating a first radio frequency carrier frequency signal (LO1), at least one second local oscillator unit (2-2, . . . 2-N, 122, 222) for generating at least one second radio frequency carrier frequency signal (LO2), a switching device (3, 103, 203) for passing on one of the radio frequency carrier frequency signals (LO1, LO2) or a zero signal (DC) in a manner dependent on a control signal (CTR), and a mixing stage (9, 109, 209, 212, 309) for mixing the signal (LO) that has been passed on by the switching device (3, 103, 203) with a mixing frequency signal (LF) to form a pulsed output signal (RFOUT), the pulsed output signal (RFOUT) having frequency pulses at a respective frequency (f1, . . . f8) and length (Tp) in a manner dependent on the control signal (CTR).

Abstract: A traveling wave amplifier comprises a first normally off MOS transistor having a drain, source and gate terminal. The drain terminal is connected to a node of a drain line, which is connected to a first supply voltage potential via a connecting resistor. The gate terminal is connected to a node of a gate line, onto which an input signal is coupled. The source terminal is coupled to a second supply voltage potential via a first resistor. The traveling wave amplifier also comprises at least one second normally off MOS transistor. In addition, the traveling wave amplifier further comprises a normally off bias MOS transistor. The normally off bias MOS transistor forms a current mirror with at least one of the second normally off MOS transistors. An output signal of the traveling wave amplifier is tapped off on the drain line.

Abstract: A current source circuit for generating a low-noise current has a current mirror circuit with a first and a second transistor. The current mirror circuit contains a capacitor connected between a source connection and a gate connection of the second transistor. The current mirror circuit likewise contains a switching element disposed between a drain connection of the first transistor and the gate connection of the second transistor. The switching element may be controlled as a function of an operating state of the current source circuit.