Abstract: Systems, apparatuses, and methods related to organizing data to correspond to a matrix at a memory device are described. Data can be organized by circuitry coupled to an array of memory cells prior to the processing resources executing instructions on the data. The organization of data may thus occur on a memory device, rather than at an external processor. A controller coupled to the array of memory cells may direct the circuitry to organize the data in a matrix configuration to prepare the data for processing by the processing resources. The circuitry may be or include a column decode circuitry that organizes the data based on a command from the host associated with the processing resource. For example, data read in a prefetch operation may be selected to correspond to rows or columns of a matrix configuration.

Abstract: Apparatuses, systems, and methods related to memory pooling between selected memory resources are described. A system using a memory pool formed as such may enable performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on increased access to data that may improve performance of a mission profile. For instance, one apparatus described herein includes a memory resource, a processing resource coupled to the memory resource, and a transceiver resource coupled to the processing resource. The memory resource, the processing resource, and the transceiver resource are configured to enable formation of a memory pool between the memory resource and another memory resource at another apparatus responsive to a request to access the other memory resource transmitted from the processing resource via the transceiver.

Abstract: Systems, apparatuses and method related to remotely executable instructions are described. A device may be wirelessly coupled to (e.g., physically separated) another device, which may be in a physically separate device. The another device may remotely execute instructions associated with performing various operations, which would have been entirely executed at the device absent the another device. The outputs obtained as a result of the execution may be transmitted, via the transceiver, back to the device via a wireless communication link (e.g., using resources of an ultra high frequency (UHF), super high frequency (SHF), extremely high frequency (EHF), and/or tremendously high frequency (THF) bands). The another device at which the instructions are remotely executable may include memory resources, processing resources, and transceiver resources; they may be configured to use one or several communication protocols over licensed or shared frequency spectrum bands, directly (e.g.

Abstract: The present disclosure includes apparatuses and methods for simultaneous in data path compute operations. An apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. A plurality of shared I/O lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. The first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period.

Abstract: Devices and methods related to spiking neural units in memory. One device includes a memory array and a complementary metal-oxide semiconductor (CMOS) coupled to the memory array and located under the memory array, wherein the CMOS includes a spiking neural unit comprising logic configured to receive an input to increase a weight stored in a memory cell of the memory array, collect the weight from the memory cell of the memory array, accumulate the weight with an increase based on the input, compare the accumulated weight to a threshold weight, and provide an output in response to the accumulated weight being greater than the threshold weight.

Abstract: Apparatuses and methods can be related to preventing the activation of rows using fuses in, for example, a memory device or a computing system that includes a memory device. The preventing the activation of rows adjacent to a predefined row address range can reduce the charge leakage from the memory cells comprising the predefined row address range. Reducing the charge leakage from memory cells comprising the predefined row address range can increase stability in data retention.

Abstract: The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

Abstract: The present disclosure includes apparatuses and methods for compute in data path. An example apparatus includes an array of memory cells. Sensing circuitry is coupled to the array of memory cells. A shared input/output (I/O) line provides a data path associated with the array. The shared I/O line couples the sensing circuitry to a compute component in the data path of the shared I/O line.

Abstract: The present disclosure includes apparatuses and methods for performing operations by a memory device in a self-refresh state. An example includes an array of memory cells and a controller coupled to the array of memory cells. The controller is configured to direct performance of compute operations on data stored in the array when the array is in a self-refresh state.

Abstract: The present disclosure is related to performing speculation in, for example, a memory device or a computing system that includes a memory device. Speculation can be used to identify data that is accessed together or to predict data that will be accessed with greater frequency. The identified data can be organized to improve efficiency in providing access to the data.

Abstract: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing transceivers, receivers, and/or transmitters of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided via a plurality of transceivers of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.

Abstract: Systems, apparatuses, and methods related to a computing tile are described. The computing tile may perform operations on received data to extract some of the received data. The computing tile may perform operations without intervening commands. The computing tile may perform operations on data streamed through the computing tile to extract relevant data from data received by the computing tile. In an example, the computing tile is configured to receive a command to initiate an operation to reduce a size of a block of data from a first size to a second size. The computing tile can then receive a block of data from a memory device coupled to the apparatus. The computing tile can then perform an operation on the block of data to extract predetermined data from the block of data to reduce a size of the block of data from a first size to a second size.

Abstract: Apparatuses and methods can be related to supplementing AI processing in memory. An accelerator and/or a host can perform AI processing. Some of the operations comprising the AI processing can be performed by a memory device instead of by an accelerator and/or a host. The memory device can perform AI processing in conjunction with the host and/or accelerator to increase the efficiency of the host and/or accelerator.

Abstract: Systems, apparatuses, and methods related to comparison of biometric identifiers in memory are described. An example apparatus includes an array of memory cells, a plurality of logic blocks in complementary metal-oxide-semiconductor (CMOS) under the array, and a controller coupled to the array of memory cells. The controller is configured to control a first portion of the plurality of logic blocks to receive a first subset of a set of biometric identifiers from the array and to perform a first comparison operation thereon and control a second portion of the logic blocks to receive a second subset of the set of biometric identifiers from the array and to perform a second comparison operation thereon. The first and second subsets of the biometric identifiers are different biometric identifiers and the first and second comparison operations are performed to determine a match of the first and second subsets respectively to a stored template.

Abstract: The present disclosure includes apparatuses and methods for data movement. An example apparatus includes a memory device that includes a plurality of subarrays of memory cells and sensing circuitry coupled to the plurality of subarrays. The sensing circuitry includes a sense amplifier and a compute component. The memory device also includes a plurality of subarray controllers. Each subarray controller of the plurality of subarray controllers is coupled to a respective subarray of the plurality of subarrays and is configured to direct performance of an operation with respect to data stored in the respective subarray of the plurality of subarrays. The memory device is configured to move a data value corresponding to a result of an operation with respect to data stored in a first subarray of the plurality of subarrays to a memory cell in a second subarray of the plurality of subarrays.

Abstract: The present disclosure includes apparatuses and methods for data movement. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array via a plurality of sense lines. The sensing circuitry includes a sense amplifier and a compute component coupled to a sense line and configured to implement operations. A controller in the memory device is configured to couple to the array and sensing circuitry. A shared I/O line in the memory device is configured to couple a source location to a destination location.

Abstract: Systems, apparatuses, and methods related to multiple artificial neural networks (ANNs) in memory. Such ANNs can be implemented within a memory system (including a number of memory devices) at different granularities. For example, multiple ANNs can be implemented within a single memory device and/or a single ANN can be implemented over multiple memory devices (such that multiple memory devices are configured as a single ANN). The memory system having multiple ANNs can operate each ANN independently from each other such that multiple ANN operations can be concurrently performed.

Abstract: A wafer-on-wafer formed memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. The memory die can be formed as one of many memory dies on a first semiconductor wafer. The logic die can be formed as one of many logic dies on a second semiconductor wafer. The first and second wafers can be bonded via a wafer-on-wafer bonding process. The memory and logic device can be singulated from the bonded first and second wafers.

Abstract: A memory device includes an array of memory cells configured on a die or chip and coupled to sense lines and access lines of the die or chip and a respective sense amplifier configured on the die or chip coupled to each of the sense lines. Each of a plurality of subsets of the sense lines is coupled to a respective local input/output (I/O) line on the die or chip for communication of data on the die or chip and a respective transceiver associated with the respective local I/O line, the respective transceiver configured to enable communication of the data to one or more device off the die or chip.

Abstract: A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. Memory devices can be formed on a first wafer. First metal pads can be formed on the first wafer and coupled to the memory devices. The memory devices can be tested via the first metal pads. The first metal pads can be removed from the first wafer. Subsequently, second metal pads on the first wafer can be bonded, via a wafer-on-wafer bonding process, to third metal pads on a second wafer. Each memory device on the first wafer can be aligned with and coupled to a respective logic device on the second wafer.