Patents by Inventor Gregg Higashi
Gregg Higashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11393683Abstract: Aspects of the disclosure relate to processes for epitaxial growth of Group III/V materials at high rates, such as about 30 ?m/hr or greater, for example, about 40 ?m/hr, about 50 ?m/hr, about 55 ?m/hr, about 60 ?m/hr, about 70 ?m/hr, about 80 ?m/hr, and about 90-120 ?m/hr deposition rates. The Group III/V materials or films may be utilized in solar, semiconductor, or other electronic device applications. The Group III/V materials may be formed or grown on a sacrificial layer disposed on or over the support substrate during a vapor deposition process. Subsequently, the Group III/V materials may be removed from the support substrate during an epitaxial lift off (ELO) process. The Group III/V materials are thin films of epitaxially grown layers containing gallium arsenide, gallium aluminum arsenide, gallium indium arsenide, gallium indium arsenide nitride, gallium aluminum indium phosphide, phosphides thereof, nitrides thereof, derivatives thereof, alloys thereof, or combinations thereof.Type: GrantFiled: September 27, 2017Date of Patent: July 19, 2022Assignee: UTICA LEASECO, LLCInventors: Lori D. Washington, David P. Bour, Gregg Higashi, Gang He
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Patent number: 11271128Abstract: An optoelectronic semiconductor device is disclosed. The device comprises a plurality of stacked p-n junctions (e.g., multi junction device). The optoelectronic semiconductor device includes a n-doped layer disposed below the p-doped layer to form a p-n layer such that electric energy is created when photons are absorbed by the p-n layer. Recesses are formed on top of the p-doped layer at the top of the plurality of stacked p-n junctions. The junctions create an offset and an interface layer is formed on top of the p-doped layer at the top of the plurality stacked p-n junctions. The device also includes a window layer disposed below the plurality stacked p-n junctions. In another aspect, one or more optical filters are inserted into a device to enhance its efficiency through photon recycling. The device can be fabricated by epitaxial growth on a substrate and removed from the substrate through a lift off process.Type: GrantFiled: September 15, 2017Date of Patent: March 8, 2022Assignee: UTICA LEASECO, LLCInventors: Brendan M. Kayes, Gang He, Sylvia Spruytte, I-Kang Ding, Gregg Higashi
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Patent number: 10768501Abstract: A tiled electrochromic (EC) device comprises a carrier glass, a first EC panel laminated to the carrier glass, a second EC panel laminated to the carrier glass, and a seam between the first EC panel and second EC panel. The first and second EC panels comprise an active area, a clear state and a dark state, and the tiled EC device is capable of switching between a clear state and a dark state.Type: GrantFiled: June 29, 2018Date of Patent: September 8, 2020Assignee: KINESTRAL TECHNOLOGIES, INC.Inventors: Sam Bergh, Howard Turner, Gregg Higashi, Paul Nagel, Wally Barnum
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Patent number: 10718051Abstract: An example method for chemical vapor deposition (CVD) of thin films includes providing a deposition zone in a reaction chamber having a fixed showerhead assembly that introduces CVD reactive gases under positive pressure into the deposition zone. The example method also includes moving a substrate carrier beneath the showerhead assembly in the reaction chamber, the substrate carrier supports and transports at least one substrate within the reaction chamber so as to be subjected to a CVD process by the CVD reactive gases. The example method also includes providing a liner assembly shrouding the deposition zone and including at least one partial enclosure around the deposition zone isolating the deposition zone and the substrate carrier, whereby solid reaction byproducts are plated onto material in the liner assembly and gaseous reaction byproducts flow radially outward, the liner assembly being mounted on the substrate carrier for motion with the substrate carrier.Type: GrantFiled: May 4, 2018Date of Patent: July 21, 2020Assignee: ALTA DEVICES, INC.Inventors: Gregg Higashi, Khurshed Sorabji, Lori D. Washington
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Patent number: 10505058Abstract: Methods and apparatus are provided for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells. One embodiment of the present invention provides a photovoltaic (PV) device. The PV device comprises an absorber layer made of a compound semiconductor; and an emitter layer located closer than the absorber layer to a first side of the device. The PV device includes a p-n junction formed between the emitter layer and the absorber layer, the p-n junction causing a voltage to be generated in the device in response to the device being exposed to light at a second side of the device. Such innovations may allow for greater efficiency and flexibility in PV devices when compared to conventional solar cells.Type: GrantFiled: May 6, 2019Date of Patent: December 10, 2019Assignee: ALTA DEVICES, INC.Inventors: Melissa J. Archer, Thomas J. Gmitter, Gang He, Gregg Higashi
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Publication number: 20190259888Abstract: Methods and apparatus are provided for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells. One embodiment of the present invention provides a photovoltaic (PV) device. The PV device comprises an absorber layer made of a compound semiconductor; and an emitter layer located closer than the absorber layer to a first side of the device. The PV device includes a p-n junction formed between the emitter layer and the absorber layer, the p-n junction causing a voltage to be generated in the device in response to the device being exposed to light at a second side of the device. Such innovations may allow for greater efficiency and flexibility in PV devices when compared to conventional solar cells.Type: ApplicationFiled: May 6, 2019Publication date: August 22, 2019Inventors: Melissa J. ARCHER, Thomas J. GMITTER, Gang HE, Gregg HIGASHI
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Publication number: 20190221698Abstract: An optoelectronic device is disclosed. The optoelectronic device comprises a semiconductor structure; a plurality of contacts on the front side of the semiconductor structure; and a plurality of non-continuous metal contacts on a back side of the semiconductor structure. In an embodiment, a plurality of non-continuous back contacts on an optoelectronic device improve the reflectivity and reduce the losses associated with the back surface of the device.Type: ApplicationFiled: November 16, 2018Publication date: July 18, 2019Inventors: Brendan M. KAYES, Sylvia SPRUYTTE, I-Kang DING, Rose TWIST, Gregg HIGASHI
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Patent number: 10326033Abstract: Methods and apparatus are provided for converting electromagnetic radiation, such as solar energy, into electric energy with increased efficiency when compared to conventional solar cells. One embodiment of the present invention provides a photovoltaic (PV) device. The PV device comprises an absorber layer made of a compound semiconductor; and an emitter layer located closer than the absorber layer to a first side of the device. The PV device includes a p-n junction formed between the emitter layer and the absorber layer, the p-n junction causing a voltage to be generated in the device in response to the device being exposed to light at a second side of the device. Such innovations may allow for greater efficiency and flexibility in PV devices when compared to conventional solar cells.Type: GrantFiled: February 20, 2013Date of Patent: June 18, 2019Assignee: ALTA DEVICES, INC.Inventors: Melissa J. Archer, Thomas J. Gmitter, Gang He, Gregg Higashi
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Publication number: 20190109261Abstract: An optoelectronic device is disclosed. The optoelectronic device comprises a semiconductor structure; a plurality of contacts on the front side of the semiconductor structure; and a plurality of non-continuous metal contacts on a back side of the semiconductor structure. In an embodiment, a plurality of non-continuous back contacts on an optoelectronic device improve the reflectivity and reduce the losses associated with the back surface of the device.Type: ApplicationFiled: November 21, 2018Publication date: April 11, 2019Inventors: Brendan C. KAYES, Sylvia SPRUYTTE, I-Kang DING, Rose TWIST, Gregg HIGASHI
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Publication number: 20190097087Abstract: An optoelectronic device is disclosed. The optoelectronic device comprises a semiconductor structure; a plurality of contacts on the front side of the semiconductor structure; and a plurality of non-continuous metal contacts on a back side of the semiconductor structure. In an embodiment, a plurality of non-continuous back contacts on an optoelectronic device improve the reflectivity and reduce the losses associated with the back surface of the device.Type: ApplicationFiled: November 21, 2018Publication date: March 28, 2019Inventors: Brendan C. KAYES, Sylvia SPRUYTTE, I-Kang DING, Rose TWIST, Gregg HIGASHI
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Publication number: 20190004386Abstract: A tiled electrochromic (EC) device comprises a carrier glass, a first EC panel laminated to the carrier glass, a second EC panel laminated to the carrier glass, and a seam between the first EC panel and second EC panel. The first and second EC panels comprise an active area, a clear state and a dark state, and the tiled EC device is capable of switching between a clear state and a dark state.Type: ApplicationFiled: June 29, 2018Publication date: January 3, 2019Inventors: Sam Bergh, Howard Turner, Gregg Higashi, Paul Nagel, Wally Barnmum
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Publication number: 20180251897Abstract: A chemical vapor deposition (CVD) reactor comprises a deposition zone, a substrate carrier and a liner assembly. The deposition zone is constructed so as to have a positive pressure reactant gases fixed showerhead introducing reactant gas supporting thin film CVD deposition. The substrate carrier movably supports a substrate and the liner assembly within the deposition zone and is heated so as to be subjected to a CVD process. The liner assembly partly encloses selected portions of the deposition zone, particularly portions of the substrate carrier and thereby enclose a hot zone surrounding a substrate to be processed so as to retain heat in that zone but allows gas flow radially outwardly toward walls of a surrounding cold-wall reactor with exhaust ports surrounding the deposition zone that exhaust spent reactant gases. The liner assembly is a sink for solid reaction byproducts while gaseous reaction byproducts are pumped out at the exhaust ports.Type: ApplicationFiled: May 4, 2018Publication date: September 6, 2018Inventors: Gregg HIGASHI, Khurshed SORABJI, Lori D. WASHINGTON
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Patent number: 10066297Abstract: A showerhead for a semiconductor processing reactor formed by an array of showerhead tiles. Each showerhead tile has a plurality of process gas apertures, which may be in a central area of the tile or may extend over the entire tile. Each showerhead tile can be dimensioned for processing a respective substrate or a plurality of substrates or the array can be dimensioned for processing a substrate. An exhaust region surrounds the process gas apertures. The exhaust region has at least one exhaust aperture, and may include an exhaust slot, a plurality of connected exhaust slots or a plurality of exhaust apertures. The exhaust region surrounds the array of showerhead tiles, or a respective portion of the exhaust region surrounds the plurality of process gas apertures in each showerhead tile or group of showerhead tiles. A gas curtain aperture may be between the exhaust region and the process gas apertures of one of the showerhead tiles or adjacent to the central area of the tile.Type: GrantFiled: October 27, 2015Date of Patent: September 4, 2018Assignee: ALTA DEVICES, INC.Inventors: Gregg Higashi, Alexander Lerner, Khurshed Sorabji, Lori D. Washington, Andreas Hegedus
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Patent number: 10008628Abstract: A method for providing a textured layer in an optoelectronic device is disclosed. The method includes depositing a template layer on a first layer. The template layer has significant inhomogeneity either in thickness or in composition, or both, including the possibility of forming one or more islands to provide at least one textured surface of the island layer. The method also includes exposing the template layer and the first layer to an etching process to create or alter at least one textured surface. The altered at least one textured surface is operative to cause scattering of light.Type: GrantFiled: November 1, 2016Date of Patent: June 26, 2018Assignee: ALTA DEVICES, INC.Inventors: I-Kang Ding, Brendan M. Kayes, Rose Twist, Sylvia Spruytte, Feng Liu, Gregg Higashi, Melissa J. Archer, Gang He
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Patent number: 9982346Abstract: A chemical vapor deposition (CVD) reactor comprises a deposition zone, a substrate carrier and a liner assembly. The deposition zone is constructed so as to have a positive pressure reactant gases fixed showerhead introducing reactant gas supporting thin film CVD deposition. The substrate carrier movably supports a substrate and the liner assembly within the deposition zone and is heated so as to be subjected to a CVD process. The liner assembly partly encloses selected portions of the deposition zone, particularly portions of the substrate carrier and thereby enclose a hot zone surrounding a substrate to be processed so as to retain heat in that zone but allows gas flow radially outwardly toward walls of a surrounding cold-wall reactor with exhaust ports surrounding the deposition zone that exhaust spent reactant gases. The liner assembly is a sink for solid reaction byproducts while gaseous reaction byproducts are pumped out at the exhaust ports.Type: GrantFiled: August 31, 2011Date of Patent: May 29, 2018Assignee: ALTA DEVICES, INC.Inventors: Gregg Higashi, Khurshed Sorabji, Lori D. Washington
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Publication number: 20180019359Abstract: An optoelectronic semiconductor device is disclosed. The device comprises a plurality of stacked p-n junctions (e.g., multi junction device). The optoelectronic semiconductor device includes a n-doped layer disposed below the p-doped layer to form a p-n layer such that electric energy is created when photons are absorbed by the p-n layer. Recesses are formed on top of the p-doped layer at the top of the plurality of stacked p-n junctions. The junctions create an offset and an interface layer is formed on top of the p-doped layer at the top of the plurality stacked p-n junctions. The device also includes a window layer disposed below the plurality stacked p-n junctions. In another aspect, one or more optical filters are inserted into a device to enhance its efficiency through photon recycling. The device can be fabricated by epitaxial growth on a substrate and removed from the substrate through a lift off process.Type: ApplicationFiled: September 15, 2017Publication date: January 18, 2018Inventors: Brendan M. KAYES, Gang HE, Sylvia SPRUYTTE, I-Kang DING, Gregg HIGASHI
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Publication number: 20180019117Abstract: Aspects of the disclosure relate to processes for epitaxial growth of Group III/V materials at high rates, such as about 30 ?m/hr or greater, for example, about 40 ?m/hr, about 50 ?m/hr, about 55 ?m/hr, about 60 ?m/hr, about 70 ?m/hr, about 80 ?m/hr, and about 90-120 ?m/hr deposition rates. The Group III/V materials or films may be utilized in solar, semiconductor, or other electronic device applications. The Group III/V materials may be formed or grown on a sacrificial layer disposed on or over the support substrate during a vapor deposition process. Subsequently, the Group III/V materials may be removed from the support substrate during an epitaxial lift off (ELO) process. The Group III/V materials are thin films of epitaxially grown layers containing gallium arsenide, gallium aluminum arsenide, gallium indium arsenide, gallium indium arsenide nitride, gallium aluminum indium phosphide, phosphides thereof, nitrides thereof, derivatives thereof, alloys thereof, or combinations thereof.Type: ApplicationFiled: September 27, 2017Publication date: January 18, 2018Inventors: Lori D. WASHINGTON, David P. Bour, Gregg Higashi, Gang He
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Patent number: 9834860Abstract: Embodiments of the invention generally relate processes for epitaxial growing Group III/V materials at high growth rates, such as about 30 ?m/hr or greater, for example, about 40 ?m/hr, about 50 ?m/hr, about 55 ?m/hr, about 60 ?m/hr, or greater. The deposited Group III/V materials or films may be utilized in solar, semiconductor, or other electronic device applications. In some embodiments, the Group III/V materials may be formed or grown on a sacrificial layer disposed on or over the support substrate during a vapor deposition process. Subsequently, the Group III/V materials may be removed from the support substrate during an epitaxial lift off (ELO) process. The Group III/V materials are thin films of epitaxially grown layers which contain gallium arsenide, gallium aluminum arsenide, gallium indium arsenide, gallium indium arsenide nitride, gallium aluminum indium phosphide, phosphides thereof, nitrides thereof, derivatives thereof, alloys thereof, or combinations thereof.Type: GrantFiled: October 13, 2010Date of Patent: December 5, 2017Assignee: ALTA DEVICES, INC.Inventors: Lori D. Washington, David P. Bour, Gregg Higashi, Gang He
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Patent number: 9768329Abstract: An optoelectronic semiconductor device is disclosed. The optoelectronic device comprises a plurality of stacked p-n junctions. The optoelectronic semiconductor device includes a n-doped layer disposed below the p-doped layer to form a p-n layer such that electric energy is created when photons are absorbed by the p-n layer. Recesses are formed on top of the p-doped layer at the top of the plurality of stacked p-n junctions. The junctions create an offset and an interface layer is formed on top of the p-doped layer at the top of the plurality stacked p-n junctions. The optoelectronic semiconductor device also includes a window layer disposed below the plurality stacked p-n junctions. In another aspect, one or more optical filters are inserted into a multi-junction photovoltaic device to enhance its efficiency through photon recycling.Type: GrantFiled: December 4, 2012Date of Patent: September 19, 2017Assignee: ALTA DEVICES, INC.Inventors: Brendan M. Kayes, Gang He, Sylvia Spruytte, I-Kang Ding, Gregg Higashi
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Patent number: 9711671Abstract: System and method of providing a photovoltaic (PV) cell with a complex via structure in the substrate that has a primary via for containing a conductive material and an overflow capture region for capturing an overflow of the conductive material from the primary via. The conductive filling in the primary via may serve as an electrical contact between the PV cell and another PV cell. The overflow capture region includes one or more recesses formed on the substrate back surface. When the conductive material overflows from the primary via, the one or more recesses can capture and confine the overflow within the boundary of the complex via structure. A recess may be a rectangular or circular trench proximate to or overlaying the primary via. The recesses may also be depressions formed by roughening the substrate back surface.Type: GrantFiled: September 18, 2015Date of Patent: July 18, 2017Assignee: ALTA DEVICES, INC.Inventors: Linlin Yang, Gang He, Dan Patterson, Paul Goddu, Liguang Lan, Gregg Higashi