Abstract: A redundant and fault tolerant solid state disk (SSD) includes a determination module configured to identify a first solid state disk controller (SSDC) configured to connect to a flash array and a second SSDC configured to connect to the flash array. A capture module is configured to capture a copy of an I/O request received by the first SSDC from a port of a dual port connector, and/or capture a copy of an I/O request received by the second SSDC from a port of the dual port connector, and identify a write I/O request from the I/O request. A detection module is configured to detect a failure in the first SSDC. A management module is configured to manage access to a flash array by the first SSDC and the second SSDC. An error recovery and failover module is configured to automatically reassign work from the first SSDC to the second SSDC.

Abstract: A mechanism is provided for firehose dumping modified data in a static random access memory of a hard disk drive to non-volatile memory of the hard disk drive during a power event. Responsive an indication of a power event in the hard disk drive, hard disk drive command processing is suspended. A token is set in the non-volatile storage indicating that flash memory in the non-volatile memory contains modified data. A portion of a static random access memory cache table containing information on the modified data in the static random access memory is copied to the flash memory. The modified data from the static random access memory is then copied to the flash memory. Responsive to a determination that the power event that initiated the copy of the modified data in the static random access memory to the flash memory is still present, the hard disk drive is shut down.

Abstract: The advanced management module services in a data processing system are configured to determine the system load and provide an input to the early power off warning detection logic that evaluates the power system state to detect a condition when power resources are insufficient to maintain the write caching storage system power within defined acceptable limits. The early power off warning detection logic generates a notification based on the system load and the available power supply resources to maintain maximum availability and reliability characteristics.

Abstract: A memory system has mechanisms for scavenging capacity of a super capacitor by removing, or reducing, system load from the super capacitor when the super capacitor voltage decays below a low threshold. The mechanisms then restore the system load to the super capacitor when the super capacitor voltage ramps back above a high threshold. A controller may reduce system load by placing a volatile memory system in a standby state and disabling a field effect transistor to remove power from a non-volatile memory system. A controller may adjust the high threshold and/or a low threshold by setting a digitally controlled potentiometer in a threshold detect circuit via an I2C bus.

Abstract: A method, system and computer-usable medium are disclosed for providing management of serial attached small computer system interface (SAS) storage devices. A host computer comprises a storage controller connected to a SAS port expander comprising a plurality of ports that are logically assigned to target storage devices. The device ports of all storage devices physically attached to the SAS port expander are bypassed to remove their logical SAS expander port assignments. The storage controller unbypasses the device ports, allowing it to recognize the presence of all physically attached storage devices. The recognized storage devices are inventoried and storage devices that are not logically assigned a SAS expander port are designated as being spare storage devices. SAS expander ports are logically assigned to the non-spare storage devices and SAS storage operations are performed.

Abstract: A mechanism is provided for autonomic component service state management for a multiple function component. The mechanism determines whether independent functions within a multiple function service boundary can be serviced. When a single function experiences a failure that requires service, repair, or replacement, the surviving functions notify the service management software of the state of the independent functions. The service management software then determines the state of the overall component and implements the appropriate service method.

Abstract: A mechanism for in situ verification of capacitive power support is provided. A memory system uses a super capacitor to support a voltage rail when input power is lost or interrupted. The voltage discharge curve is a function of load and capacitance of the component. By stepping the regulated power supply to a lower output within the voltage range and recording voltage and current draw at the super capacitor as it discharges to the new regulator output voltage, the super capacitor holdup capability can be tested.

Abstract: A controller of a memory system is configured to reduce power requirements during memory backup transition. When transitioning to backup mode, the memory system controller performs a number of power saving techniques. The controller may change a number of configuration settings in the volatile memory system, such as reducing output driver strength, increasing differential impedance, increasing on-die termination, disabling receiver input circuitry, and disconnecting the termination voltage network. The controller may also assert a hard reset to the storage controller system to significantly reduce the load and allow the voltage regulator to continue to provide power to the memory system for a longer period of time.

Abstract: To ensure integrity of non-volatile flash, the controller programs the non-volatile memories with background test patterns and verifies the non-volatile memories during power on self test (POST) operation. In conjunction with verifying the non-volatile memories, the controller may routinely run diagnostics and report status to the storage controller. As part of the storage controller power up routines, the storage controller issues a POST command to the controller via an I2C register that is monitored by the storage controller. The storage controller may determine that the non-volatile flash is functional without any defects, and the controller may remove power from the non-volatile flash to extend its reliability. Periodically, in the background, the controller may run diagnostic routines to detect any failures associated with the volatile memory and the controller itself.

Abstract: A method is disclosed to set the speed of a network. The method supplies a network interconnected with a system controller and a plurality of switch domains, where each of those plurality of switch domains comprises one or more information storage devices and a switch domain controller, and sets by each of the plurality of switch domains a signaling rate for that switch domain. The method queries in-band by the system controller each of the plurality of switch domains for that switch domain's signaling rate, and provides in-band by each of the plurality of switch domains the signaling rate for that switch domain. The method provides in-band by the system controller to each of the plurality of switch domains a first speed selection command specifying a first network speed, and resets by each of the plurality of switch domains the signaling rate for that switch domain to the first network speed.

Abstract: An electronics component support assembly and an electronics system assembly employing the component support assembly are provided. The component support assembly includes a rotatable base support and a component connector assembly. The rotatable base support is sized to reside within an electronics enclosure and to operatively support multiple electronics components thereon. The component connector assembly is associated with the rotatable base support, and at least some electronics components of the multiple electronics components couple thereto when operatively supported by the rotatable base support. Rotation of the rotatable base support facilitates access to the multiple electronics components, and the component connector assembly allows for rotation of the rotatable base support with the multiple electronics components operatively supported on the rotatable base support.

Abstract: A method for flash sparing on a solid state drive (SSD) includes detecting a failure from a primary memory device; determining if a failure threshold for the primary memory device has been reached; and, in the event the failure threshold for the primary memory device has been reached: quiescing the SSD; and updating an entry in a sparing map table to replace the primary memory device with a spare memory device.

Abstract: A method to provide an operation to an information storage device is disclosed. The method supplies an information storage device and a protocol conversion device capable of receiving an operation in a first communication protocol comprising a variable attribute, and providing that operation to the information storage device in a second communication protocol, where that second communication protocol does not support the variable attribute. The method provides an operation to the protocol conversion device using said first communication protocol, and determines if the variable attribute is configured in that operation. If the method determines that the variable attribute is not configured in the operation, then the method provides the operation to the information storage device using the second communication protocol.

Abstract: A redundant and fault tolerant solid state disk (SSDC) includes a determination module configured to identify a first SSDC configured to connect to a flash array and a second SSDC configured to connect to the flash array. A capture module is configured to capture a copy of an I/O request received by the first SSDC from a port of a dual port connector, and/or capture a copy of an I/O request received by the second SSDC from a port of the dual port connector, and identify a write I/O request from the I/O request. A detection module is configured to detect a failure in the first SSDC. A management module is configured to manage access to a flash array by the first SSDC and the second SSDC. An error recovery and failover module is configured to automatically reassign work from the first SSDC to the second SSDC.

Abstract: Systems and methods for monitoring high-speed network traffic via sequentially multiplexed data streams. Exemplary embodiments include a switch module system, including a first switch module configured to be coupled to a first server chassis, a first data port disposed on the first switch module and a set of first port data links configured to be coupled to a set of data port data links, each data link configurable to channel at least one of a normal data stream and a monitored data stream.

Abstract: A method for adjusting a drive life and a capacity of a solid state drive (SSD), the SSD comprising a plurality of memory devices includes determining a desired drive life for the SSD; determining a utilization for the SSD; and allocating a portion of the plurality of memory devices as available memory and a portion of the plurality of memory devices as spare memory based on the desired drive life and the utilization. An SSD with an adjustable drive life and capacity includes a plurality of memory devices; and a memory allocation module configured to: determine a desired drive life for the SSD; determine a utilization for the SSD; and allocate a portion of the plurality of memory devices as available memory and a portion of the plurality of memory devices as spare memory based on the desired drive life and the utilization.

Abstract: A method for flash sparing on a solid state drive (SSD) includes detecting a failure from a primary memory device; determining if a failure threshold for the primary memory device has been reached; and, in the event the failure threshold for the primary memory device has been reached: quiescing the SSD; and updating an entry in a sparing map table to replace the primary memory device with a spare memory device.

Abstract: A data storage and retrieval system that comprises a data storage device is disclosed. The data storage and retrieval system further comprises a first LED, a second LED, a third LED, and a fourth LED, interconnected with the data storage device. The data storage device causes the first LED and the second LED to emit first light comprising a first color if the data storage device detects an internal failure. Alternatively, the storage device causes the third LED and the fourth LED to emit second light comprising a second color if the data storage device remains operative.

Abstract: A system migrates data between a source device and a target device in a storage system. A processor is operational within a local domain of the storage system. A redundant array of independent disks (RAID) controller electrically connected to the processor. The RAID controller divides a capacity of the source device into a plurality of sub-regions, locks the sub-regions from storage activity, establishes a mirroring relationship for write data updates between the source device and target device, and assigns the processor to copy data from the source device to the target device. A method of migrating data includes dividing a capacity of a source device into a plurality of sub-regions, locking the sub-regions from storage activity, establishing a mirroring relationship for write data updates between the source device and a target device, and assigning a local processor to copy data from the source device to the target device.

Abstract: A method for automatically detecting and correcting one or more hang conditions within one or more of a master device and target device of a serial bus interface when one or more signals are held in an invalid state. A hang timer monitors one or more operations of the serial bus when the serial bus is participating in a serial bus transfer. If the transfer does not end before the bus timeout value has been exceeded, the hang timer will issue a reset to the state machine forcing the state machine back to an idle state. The hang timer will also disable the serial bus drivers of the state machine, whereby the hang condition is corrected.