Patents by Inventor Gregor Keller

Gregor Keller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200350408
    Abstract: A stacked high barrier III-V power semiconductor diode having an at least regionally formed first metallic terminal contact layer and a heavily doped semiconductor contact region of a first conductivity type with a first lattice constant, a drift layer of a second conductivity type, a heavily doped metamorphic buffer layer sequence of the second conductivity type is formed. The metamorphic buffer layer sequence has an upper side with the first lattice constant and a lower side with a second lattice constant. The first lattice constant is greater than the second lattice constant. The upper side of the metamorphic buffer layer sequence is arranged in the direction of the drift layer. A second metallic terminal contact layer is arranged below the lower side of the metamorphic buffer layer sequence. The second metallic terminal contact layer is integrally bonded with a semiconductor contact layer.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 5, 2020
    Applicant: AZUR SPACE Solar Power GmbH
    Inventors: Daniel FUHRMANN, Gregor KELLER, Clemens WAECHTER
  • Publication number: 20200350407
    Abstract: A stacked, high-blocking III-V semiconductor power diode having a first metallic terminal contact layer, formed at least in regions, and a highly doped semiconductor contact region of a first conductivity type and a first lattice constant. A drift layer of a second conductivity type and having a first lattice constant is furthermore provided. A semiconductor contact layer of a second conductivity, which includes an upper side and an underside, and a second metallic terminal contact layer are formed, and the second metallic terminal contact layer being integrally connected to the underside of the semiconductor contact layer, and the semiconductor contact layer having a second lattice constant at least on the underside, and the second lattice constant being the lattice constant of InP, and the drift layer and the highly doped semiconductor contact region each comprising an InGaAs compound or being made up of InGaAs.
    Type: Application
    Filed: April 30, 2020
    Publication date: November 5, 2020
    Applicants: AZUR SPACE Solar Power GmbH, 3-5 Power Electronics GmbH
    Inventors: Daniel FUHRMANN, Gregor KELLER, Clemens WAECHTER, Volker DUDEK
  • Patent number: 10600929
    Abstract: An optical voltage source and decoupling device is provided, wherein the optical voltage source has a number N of series-connected semiconductor diodes, each having a p-n junction, the semiconductor diodes are monolithically integrated and together form a first stack with an upper side and an underside, and the number N of the semiconductor diodes of the first stack is greater than or equal to two, the decoupling device has a further semiconductor diode. The further semiconductor diode has a pin junction and, the further semiconductor diode is anti-serially connected with the semiconductor diodes of the first stack. An underside of the further semiconductor diode is materially connected with the upper side of the first stack and the further semiconductor diode forms a total stack together with the first stack.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: March 24, 2020
    Assignee: Azur Space Solar Power GmbH
    Inventors: Gregor Keller, Daniel Fuhrmann
  • Patent number: 10388819
    Abstract: A receiver unit having an optically operated voltage source, the voltage source including a first stack having an upper side and an underside and being formed on an upper side of a non-Si substrate based on III-V semiconductor layers arranged in the shape of a stack, and having a second electrical terminal contact on the upper side of the first stack and a first electrical terminal contact on an underside of the non-Si substrate, a voltage generated with the aid of the incidence of light onto the upper side of the first stack being present between the two terminal contacts, and including a second stack having a MOS transistor structure having III-V semiconductor layers and including a control terminal and a drain terminal and a source terminal. The MOS transistor structure being designed as a depletion field effect transistor.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: August 20, 2019
    Assignee: AZUR SPACE SOLAR POWER GMBH
    Inventors: Daniel Fuhrmann, Thomas Lauermann, Gregor Keller
  • Publication number: 20190189825
    Abstract: An optical voltage source and decoupling device is provided, wherein the optical voltage source has a number N of series-connected semiconductor diodes, each having a p-n junction, the semiconductor diodes are monolithically integrated and together form a first stack with an upper side and an underside, and the number N of the semiconductor diodes of the first stack is greater than or equal to two, the decoupling device has a further semiconductor diode. The further semiconductor diode has a pin junction and, the further semiconductor diode is anti-serially connected with the semiconductor diodes of the first stack. An underside of the further semiconductor diode is materially connected with the upper side of the first stack and the further semiconductor diode forms a total stack together with the first stack.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 20, 2019
    Applicant: AZUR SPACE Solar Power GmbH
    Inventors: Gregor KELLER, Daniel FUHRMANN
  • Publication number: 20190058074
    Abstract: A receiver unit having an optically operated voltage source, the voltage source including a first stack having an upper side and an underside and being formed on an upper side of a non-Si substrate based on III-V semiconductor layers arranged in the shape of a stack, and having a second electrical terminal contact on the upper side of the first stack and a first electrical terminal contact on an underside of the non-Si substrate, a voltage generated with the aid of the incidence of light onto the upper side of the first stack being present between the two terminal contacts, and including a second stack having a MOS transistor structure having III-V semiconductor layers and including a control terminal and a drain terminal and a source terminal. The MOS transistor structure being designed as a depletion field effect transistor.
    Type: Application
    Filed: August 16, 2018
    Publication date: February 21, 2019
    Applicant: AZUR SPACE Solar Power GmbH
    Inventors: Daniel Fuhrmann, Thomas Lauermann, Gregor Keller