Patents by Inventor Gudrun Stranzl

Gudrun Stranzl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170076961
    Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.
    Type: Application
    Filed: November 25, 2016
    Publication date: March 16, 2017
    Inventors: Markus Zundel, Andre Schmenn, Damian Sojka, Isabella Goetz, Gudrun Stranzl, Sebastian Werner, Thomas Fischer, Carsten Ahrens, Edward Fuergut
  • Publication number: 20170076970
    Abstract: Methods for processing a semiconductor workpiece can include providing a semiconductor workpiece that includes one or more kerf regions; forming one or more trenches in the workpiece by removing material from the one or more kerf regions from a first side of the workpiece; mounting the workpiece with the first side to a carrier; thinning the workpiece from a second side of the workpiece; and forming a metallization layer over the second side of the workpiece.
    Type: Application
    Filed: November 23, 2016
    Publication date: March 16, 2017
    Inventors: Gudrun Stranzl, Martin Zgaga, Rainer Leuschner, Bernhard Goller, Bernhard Boche, Manfred Engelhardt, Hermann Wendt, Bernd Noehammer, Karl Mayer, Michael Roesner, Monika Cornelia Voerckel
  • Publication number: 20170030890
    Abstract: A microfiltration device comprises a substrate having a first surface and a second surface opposite to the first surface. The substrate includes a cavity between the first surface and the second surface. The substrate further includes a microfilter including a frame part in contact with the substrate and a filter part abutting the cavity. The microfilter comprises in both the frame part and the filter part a semiconducting or conducting material.
    Type: Application
    Filed: July 27, 2016
    Publication date: February 2, 2017
    Inventors: Gerald Holweg, Yonsuang Arnanthigo, Jan Berger, Guenter Denifl, Sylvicley Figueira Da Silva, Iris Moder, Thomas Ostermann, Alexander Oswatitsch, Vijaye Kumar Rajaraman, Gudrun Stranzl
  • Publication number: 20160379884
    Abstract: A method of dicing a wafer includes providing a wafer and etching the wafer to singulate die between kerf line segments defined within an interior region of the wafer and to singulate a plurality of wafer edge areas between the kerf line segments and a circumferential edge of the wafer. Each one of the plurality of wafer edge areas is singulated by kerf lines that each extend between one of two endpoints of one of the kerf line segments and the circumferential edge of the wafer.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 29, 2016
    Inventors: Joerg Ortner, Michael Roesner, Gudrun Stranzl, Rudolf Rothmaler
  • Patent number: 9496193
    Abstract: A semiconductor chip includes a body having a frontside, a backside opposite the frontside, and sidewalls extending between the backside and frontside, at least a portion of each sidewall having a defined surface structure with hydrophobic characteristics to inhibit travel of a bonding material along the sidewalls during attachment of the semiconductor chip to a carrier with the bonding material.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: November 15, 2016
    Assignee: Infineon Technologies AG
    Inventors: Michael Roesner, Gudrun Stranzl, Martin Zgaga, Martin Sporn, Tobias Schmidt
  • Patent number: 9490103
    Abstract: Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: November 8, 2016
    Assignee: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Gudrun Stranzl, Markus Zundel, Hubert Maier
  • Publication number: 20160322306
    Abstract: The description discloses a method for use in manufacturing integrated circuit chips. The method comprises providing a wafer having a plurality of integrated circuits each provided in an separate active areas, and, for each active area, outside the active area, providing a code pattern that is associated with the integrated circuit. A computer-readable medium is also disclosed. Further, a manufacturing apparatus configured to receive a wafer and to remove material from the wafer so as to provide a scribe line to the wafer formed as a trench for use in separation of the wafer into dies is also disclosed. The description also discloses a wafer, an integrated circuit chip die substrate originating from a wafer of origin and carrying an integrated circuit, and an integrated circuit chip.
    Type: Application
    Filed: April 28, 2015
    Publication date: November 3, 2016
    Inventors: Michael Roesner, Gudrun Stranzl, Manfred Engelhardt, Martin Zgaga
  • Patent number: 9455192
    Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes attaching a substrate to a carrier using an adhesive component and forming a through trench through the substrate to expose the adhesive component. At least a portion of the adhesive component is etched and a metal layer is formed over sidewalls of the through trench.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: September 27, 2016
    Assignee: Infineon Technologies AG
    Inventors: Michael Roesner, Manfred Engelhardt, Johann Schmid, Gudrun Stranzl, Joachim Hirschler
  • Patent number: 9449928
    Abstract: A layer arrangement in accordance with various embodiments may include: a wafer; a passivation disposed over the wafer; a protection layer disposed over at least a surface of the passivation facing away from the wafer; and a mask layer disposed over at least a surface of the protection layer facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation, and wherein the mask layer includes a material that is selectively etchable to the material of the protection layer.
    Type: Grant
    Filed: April 15, 2014
    Date of Patent: September 20, 2016
    Assignee: Infineon Technologies AG
    Inventors: Joachim Hirschler, Gudrun Stranzl
  • Patent number: 9449876
    Abstract: A method of separating individual dies of a semiconductor wafer includes forming a metal layer on a first surface of a semiconductor wafer, the semiconductor wafer including a plurality of dies, separating the plurality of dies from one another, and electrical discharge machining the metal layer into individual segments each of which remains attached to one of the dies. A corresponding semiconductor die produced by such a method is also provided.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: September 20, 2016
    Assignee: Infineon Technologies AG
    Inventors: Michael Roesner, Gudrun Stranzl, Manfred Schneegans
  • Publication number: 20160111255
    Abstract: Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts.
    Type: Application
    Filed: December 21, 2015
    Publication date: April 21, 2016
    Inventors: Manfred Engelhardt, Gudrun Stranzl, Markus Zundel, Hubert Maier
  • Patent number: 9293371
    Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: March 22, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Anja Reitmeier, Hermann Wendt, Thomas Fischer, Bernhard Weidgans, Gudrun Stranzl, Tobias Schmidt, Dietrich Bonart
  • Patent number: 9257342
    Abstract: In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: February 9, 2016
    Assignee: Infineon Technologies AG
    Inventors: Gudrun Stranzl, Martin Zgaga, Markus Kahn, Guenter Denifl
  • Patent number: 9219011
    Abstract: Various methods and apparatuses are provided relating to separation of a substrate into a plurality of parts. For example, first a partial separation is performed and then the partially separated substrate is completely separated into a plurality of parts.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: December 22, 2015
    Assignee: Infineon Technologies AG
    Inventors: Manfred Engelhardt, Gudrun Stranzl, Markus Zundel, Hubert Maier
  • Publication number: 20150294911
    Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.
    Type: Application
    Filed: June 24, 2015
    Publication date: October 15, 2015
    Inventors: Anja Reitmeier, Hermann Wendt, Thomas Fischer, Bernhard Weidgans, Gudrun Stranzl, Tobias Schmidt, Dietrich Bonart
  • Publication number: 20150279740
    Abstract: In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes attaching a substrate to a carrier using an adhesive component and forming a through trench through the substrate to expose the adhesive component. At least a portion of the adhesive component is etched and a metal layer is formed over sidewalls of the through trench.
    Type: Application
    Filed: March 26, 2014
    Publication date: October 1, 2015
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Michael Roesner, Manfred Engelhardt, Johann Schmid, Gudrun Stranzl, Joachim Hirschler
  • Publication number: 20150221523
    Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.
    Type: Application
    Filed: January 16, 2015
    Publication date: August 6, 2015
    Inventors: Markus Zundel, Andre Schmenn, Damian Sojka, Isabella Goetz, Gudrun Stranzl, Sebastian Werner, Thomas Fischer, Carsten Ahrens, Edward Fuergut
  • Publication number: 20150217997
    Abstract: A method for structuring a substrate and a structured substrate are disclosed. In an embodiment a method includes providing a substrate with a first main surface and a second main surface, wherein the substrate is fixed to a carrier arrangement at the second main surface, performing a photolithography step at the first main surface of the substrate to mark a plurality of sites at the first main surface, the plurality of sites corresponding to future perforation structures and future kerf regions for a plurality of future individual semiconductor chips to be obtained from the substrate, and plasma etching the substrate at the plurality of sites until the carrier arrangement is reached, thus creating the perforation structures within the plurality of individual semiconductor chips and simultaneously separating the individual semiconductor chips along the kerf regions.
    Type: Application
    Filed: January 31, 2014
    Publication date: August 6, 2015
    Inventors: Thomas Grille, Ursula Hedenig, Michael Roesner, Gudrun Stranzl, Martin Zgaga
  • Patent number: 9093385
    Abstract: A method for processing a semiconductor workpiece is provided, which may include: providing a semiconductor workpiece including a metallization layer stack disposed at a side of the semiconductor workpiece, the metallization layer stack including at least a first layer and a second layer disposed over the first layer, wherein the first layer contains a first material and the second layer contains a second material that is different from the first material; patterning the metallization layer stack, wherein patterning the metallization layer stack includes wet etching the first layer and the second layer by means of an etching solution that has at least substantially the same etching rate for the first material and the second material.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: July 28, 2015
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Anja Gissibl, Hermann Wendt, Thomas Fischer, Bernhard Weidgans, Gudrun Stranzl, Tobias Schmidt, Dietrich Bonart
  • Publication number: 20150206802
    Abstract: A method of separating individual dies of a semiconductor wafer includes forming a metal layer on a first surface of a semiconductor wafer, the semiconductor wafer including a plurality of dies, separating the plurality of dies from one another, and electrical discharge machining the metal layer into individual segments each of which remains attached to one of the dies. A corresponding semiconductor die produced by such a method is also provided.
    Type: Application
    Filed: January 17, 2014
    Publication date: July 23, 2015
    Inventors: Michael Roesner, Gudrun Stranzl, Manfred Schneegans