Abstract: In some embodiments, a system includes multiple access switches, a switch fabric having multiple switch fabric portions, and a control plane processor. Each switch fabric portion is coupled to at least one access switch by a cable from a first set of cables. Each switch fabric portion is configured to receive data from the at least one access switch via the cable from the first set of cables. The control plane processor is coupled to each switch fabric portion by a cable from a second set of cables. The control plane processor is configured to send control information to each access switch via a cable from the second set of cables, a switch fabric portion, and a cable from the first set of cables. The control plane processor is configured to determine control plane connections associated with each access switch and is configured to determine data plane connections associated with each access switch as a result of the control plane connections.

Abstract: In one embodiment, edge devices can be configured to be coupled to a multi-stage switch fabric and peripheral processing devices. The edge devices and the multi-stage switch fabric can collectively define a single logical entity. A first edge device from the edge devices can be configured to be coupled to a first peripheral processing device from the peripheral processing devices. The second edge device from the edge devices can be configured to be coupled to a second peripheral processing device from the peripheral processing devices. The first edge device can be configured such that virtual resources including a first virtual resource can be defined at the first peripheral processing device. A network management module coupled to the edge devices and configured to provision the virtual resources such that the first virtual resource can be migrated from the first peripheral processing device to the second peripheral processing device.

Abstract: A method of sending data to a switch fabric includes assigning a destination port of an output module to a data packet based on at least one field in a first header of the data packet. A module associated with a first stage of the switch fabric is selected based on at least one field in the first header. A second header is appended to the data packet. The second header includes an identifier associated with the destination port of the output module. The data packet is sent to the module associated with the first stage. The module associated with the first stage is configured to send the data packet to a module associated with a second stage of the switch fabric based on the second header.

Abstract: In some embodiments, an apparatus comprises a processing module, disposed within a first switch fabric element, configured to detect a second switch fabric element having a routing module when the second switch fabric element is operatively coupled to the first switch fabric element. The processing module is configured to define a virtual processing module configured to be operatively coupled to the second switch fabric element. The virtual processing module is configured to receive a request from the second switch fabric element for forwarding information and the virtual processing module is configured to send the forwarding information to the routing module.

Abstract: In some embodiments, an apparatus includes a network management module. The network management module is configured to send a request for power output data from a first network element having a first power supply configured to be coupled to a first power outlet, and a second power supply configured to be coupled to a second power outlet. The network management module is configured to receive a first confirmation from the first network element that the first power supply and the second power supply are receiving power. The network management module is configured to send a request to disable a third power outlet and to receive, after sending the request to disable the third power outlet, a second confirmation from the first network element that the first power supply and the second power supply are receiving power. The network management module is configured to define a power distribution table after receiving the second confirmation, the power distribution table designating the third power outlet as unused.

Abstract: In one embodiment, a method includes sending a configuration signal to a virtual network switch module within a control plane of a communications network. The configuration signal is configured to define a first network rule at the virtual network switch module. The method also includes configuring a packet forwarding module such that the packet forwarding module implements a second network rule, and receiving status information from the virtual network switch module and status information from the packet forwarding module. The status information is received via the control plane.

Abstract: In one embodiment, a method includes receiving a request to transmit data from a first queue to a second queue via a switch fabric. In response to the receiving, a wake-up signal configured to trigger a stage of a processing pipeline in communication with the second queue to change from a standby state to an active state is sent.

Abstract: A node is configured to receive a packet from a host device, where the packet includes a source address associated with the host device; determine that the source address is not stored by the node; generate one or more logical distances, associated with one or more nodes, based on the source address and a respective address associated with each of the nodes; determine that another node is associated with a shortest logical distance, of the one or more logical distances; and transmit the source address to the other node based on the determination that the other node is associated with the shortest logical distance, where transmitting the source address allows the other node to store the source address or enables further nodes to obtain the source address from the other node.

Abstract: A device may include multi-bank SRAM logic configured to receive an lookup result that includes a first number of addresses, parse each of the first number of addresses from the received lookup result, simultaneously provide at least one of the first number of parsed addresses to each of a first number of SRAMs, simultaneously read data from each of the first number of SRAMs and simultaneously transmit the read data from each of the first number of SRAMs.

Abstract: A node is configured to receive a packet from a host device, where the packet includes a source address associated with the host device; determine that the source address is not stored by the node; generate one or more logical distances, associated with one or more nodes, based on the source address and a respective address associated with each of the nodes; determine that another node is associated with a shortest logical distance, of the one or more logical distances; and transmit the source address to the other node based on the determination that the other node is associated with the shortest logical distance, where transmitting the source address allows the other node to store the source address or enables further nodes to obtain the source address from the other node.

Abstract: In some embodiments, an apparatus includes a first housing, a second housing and at least one cable. The first housing includes a first interface card of a switch fabric. The second housing includes a second interface card of the switch fabric and a third interface card of the switch fabric. The second interface card of the switch fabric is operatively and physically coupled to the third interface card of the switch fabric via a midplane. The second interface card defines a plane that is nonparallel to the a plane defined by the third interface card and a plane defined by the midplane. The plane defined by the third interface card is nonparallel to the plane defined by the second interface card and the plane defined by the midplane. The cable is configured to operatively couple the first interface card to the second interface card.

Abstract: In one embodiment, an apparatus includes a shared memory buffer including a lead memory bank and a write multiplexing module configured to send a leading segment from a set of segments to the lead memory bank. The set of segments includes bit values from a set of variable-sized cells. The write multiplexing module further configured to send each segment from the set of segments identified as a trailing segment to a portion of the shared memory mutually exclusive from the lead memory bank.

Abstract: In some embodiments, an apparatus includes a first housing, a second housing and at least one cable. The first housing includes a first interface card of a switch fabric. The second housing includes a second interface card of the switch fabric and a third interface card of the switch fabric. The second interface card of the switch fabric is operatively and physically coupled to the third interface card of the switch fabric via a midplane. The second interface card defines a plane that is nonparallel to the a plane defined by the third interface card and a plane defined by the midplane. The plane defined by the third interface card is nonparallel to the plane defined by the second interface card and the plane defined by the midplane. The cable is configured to operatively couple the first interface card to the second interface card.

Abstract: In some embodiments, a system includes multiple access switches, a switch fabric having multiple switch fabric portions, and a control plane processor. Each switch fabric portion is coupled to at least one access switch by a cable from a first set of cables. Each switch fabric portion is configured to receive data from the at least one access switch via the cable from the first set of cables. The control plane processor is coupled to each switch fabric portion by a cable from a second set of cables. The control plane processor is configured to send control information to each access switch via a cable from the second set of cables, a switch fabric portion, and a cable from the first set of cables. The control plane processor is configured to determine control plane connections associated with each access switch and is configured to determine data plane connections associated with each access switch as a result of the control plane connections.

Abstract: A device may include logic configured to receive a packet, identify a flow associated with the packet in a flow table, and identify a rate limit associated with the flow in the flow table. A current rate associated with the flow may be calculated based on the packet. It may be determined whether the current rate associated with the flow exceeds the rate limit associated with the flow. If so, the packet may be discarded or tagged as “over limit.

Abstract: In some embodiments, a system includes a first switch fabric device, a second switch fabric device, a first access switch operatively coupled to the first switch fabric device by a first cable, and a second access switch operatively coupled to the second switch fabric device by a second cable. The second access switch is operatively coupled to the first access switch by a third cable. The first access switch is configured to send data to the first switch fabric device via the first cable. The first access switch is configured to send data to the second switch fabric device via the third cable, the second access switch, and the second cable.

Abstract: A device may include multi-bank SRAM logic configured to receive an lookup result that includes a first number of addresses, parse each of the first number of addresses from the received lookup result, simultaneously provide at least one of the first number of parsed addresses to each of a first number of SRAMs, simultaneously read data from each of the first number of SRAMs and simultaneously transmit the read data from each of the first number of SRAMs.

Abstract: A device may include two or more line interfaces. One of the line interfaces may include a component to buffer a packet that is received at the line interface, perform a lookup of information related to selecting a flow based on a header of the packet, apply a symmetric hash function to addresses in the header to obtain a hash when the information related to selecting the flow indicates the flow is to be selected based on a random method, compare the hash to a particular number using the information related to selecting the flow, the particular number being same for the line interfaces, sample a flow when the hash matches the particular number, create a flow record for the flow, and sample packets based on the flow record.

Abstract: In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric physically distributed among a set of chassis. The multi-stage switch fabric has a set of input buffers and a set of output ports. The switch core can be configured to be coupled to a set of edge devices. The apparatus can also include a controller implemented in hardware without software during operation and with software during configuration and monitoring. The controller can be coupled to the set of input buffers and the set of output ports. The controller can be configured to send a flow control signal to an input buffer from the set of input buffers when congestion at an output port from the set of output ports is predicted and before congestion in the switch core occurs.

Abstract: In one embodiment, an apparatus includes a switch core that defines a single logical entity and has a multi-stage switch fabric physically distributed across a plurality of chassis. The multi-stage switch fabric has a plurality of ingress ports and a plurality of egress ports. The switch core is configured to be coupled to a plurality of peripheral processing devices via the plurality of ingress ports and the plurality of egress ports. The switch core is also configured to provide non-blocking connectivity at line rate between a first peripheral processing device disposed with a first chassis and a second peripheral processing device disposed within a second chassis.