Abstract: A front-to-back cooling system allows cooling of an apparatus containing two orthogonal sets of modules. Each set of modules is independently cooled. A vertical set of modules is cooled with vertical air flow across the modules that enters from a front of the apparatus and exhausts from a back of the apparatus. A horizontal set of modules is cooled with horizontal front-to-back air flow. When the horizontal set of modules is at the front of the apparatus, a plenum extending exterior to the vertical set of modules allows exhausting horizontally flowing air to the rear of the apparatus. When the horizontal set of modules is at the rear of the apparatus, a plenum extending exterior to the vertical set of modules allows moving air from the front of the apparatus to a chamber holding the horizontal modules.

Abstract: In one embodiment, an apparatus includes a shared memory buffer including a lead memory bank and a write multiplexing module configured to send a leading segment from a set of segments to the lead memory bank. The set of segments includes bit values from a set of variable-sized cells. The write multiplexing module further configured to send each segment from the set of segments identified as a trailing segment to a portion of the shared memory mutually exclusive from the lead memory bank.

Abstract: A data processing unit includes a chassis configured to contain a line card. The chassis defines, at least in part, a portion of a first flow pathway and a portion of a second flow pathway. The chassis is configured such that a first portion of a gas can flow within the first flow pathway between an intake region and the first end portion of the line card such that the first portion of the gas flows across a first end portion of the line card in a first direction. The chassis is configured such that a second portion of the gas can flow within the second flow pathway between the intake region and a second end portion of the line card such that the second portion of the gas flows across the second end portion of the line card in a second direction opposite the first direction.

Abstract: A device may receive a fragment of a fragmented data unit, determine a flow identifier that identifies a data flow with which the fragment is associated, and create a flow entry, based on the flow identifier, to store information associated with the data flow. The device may also determine a fragment key associated with the fragment, store a pointer to the flow entry based on the fragment key, correlate the fragment and another fragment, associated with the data flow, based on the fragment key and the pointer to the flow entry, and accumulate statistics associated with the fragment and the other fragment after correlating the fragment and the other fragment.

Abstract: In some embodiments, an apparatus includes a first housing, a second housing and at least one cable. The first housing includes a first interface card of a switch fabric. The second housing includes a second interface card of the switch fabric and a third interface card of the switch fabric. The second interface card of the switch fabric is operatively and physically coupled to the third interface card of the switch fabric via a midplane. The second interface card defines a plane that is nonparallel to the a plane defined by the third interface card and a plane defined by the midplane. The plane defined by the third interface card is nonparallel to the plane defined by the second interface card and the plane defined by the midplane. The cable is configured to operatively couple the first interface card to the second interface card.

Abstract: In some embodiments, an apparatus includes a first housing, a second housing and at least one cable. The first housing includes a first interface card of a switch fabric. The second housing includes a second interface card of the switch fabric and a third interface card of the switch fabric. The second interface card of the switch fabric is operatively and physically coupled to the third interface card of the switch fabric via a midplane. The second interface card defines a plane that is nonparallel to the a plane defined by the third interface card and a plane defined by the midplane. The plane defined by the third interface card is nonparallel to the plane defined by the second interface card and the plane defined by the midplane. The cable is configured to operatively couple the first interface card to the second interface card.

Abstract: Reversible airflow in cooling systems of electronic devices is described. For example, an electronic device may include a reversible fan tray. The fan tray may include symmetric mounting features that allow the fan tray to be mounted in the electronic device in more than one orientation at the same location within the electronic device such that one or more fans in the fan tray either direct air into the electronic device or to pull air from electronic device. The fan tray may further include a symmetric arrangement of connectors that coincide with the symmetric arrangement of mounting features to allow the fan tray to be connected to a power source of the electronic device any of the more than one orientations. An arrangement of electronic devices including reversible fan trays may be configured so that inlet and outlet airflows are separated to increase cooling efficiency of the electronic devices.

Abstract: A device provides a flow table. The device receives a data unit, determines a data flow associated with the data unit, determines whether the flow table includes an entry corresponding to the data flow, determines a current utilization of a group of output ports of the device, selects an output port, of the group of output ports, for the data flow based on the current utilization of the group of output ports when the flow table does not store an entry corresponding to the data flow, and stores the data unit in a queue associated with the selected output port.

Abstract: In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric. The multi-stage switch fabric has a set of ingress ports and a set of egress ports. The switch core can be configured to be coupled to a set of edge devices via the set of ingress ports and the set of egress ports. The switch core can be configured to receive a packet from an ingress port from the set of ingress ports. The switch core can be configured to send a set of cells associated with the packet from the ingress port to an egress port from the set of egress ports without a store-and-forward delay associated with a zero-load latency for the switch core.

Abstract: In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric physically distributed among a set of chassis. The multi-stage switch fabric has a set of input buffers and a set of output ports. The switch core can be configured to be coupled to a set of edge devices. The apparatus can also include a controller implemented in hardware without software during operation and with software during configuration and monitoring. The controller can be coupled to the set of input buffers and the set of output ports. The controller can be configured to send a flow control signal to an input buffer from the set of input buffers when congestion at an output port from the set of output ports is predicted and before congestion in the switch core occurs.

Abstract: In one embodiment, an apparatus includes a switch core that defines a single logical entity and has a multi-stage switch fabric physically distributed across a plurality of chassis. The multi-stage switch fabric has a plurality of ingress ports and a plurality of egress ports. The switch core is configured to be coupled to a plurality of peripheral processing devices via the plurality of ingress ports and the plurality of egress ports. The switch core is also configured to provide non-blocking connectivity at line rate between a first peripheral processing device disposed with a first chassis and a second peripheral processing device disposed within a second chassis.

Abstract: In one embodiment, edge devices can be configured to be coupled to a multi-stage switch fabric and peripheral processing devices. The edge devices and the multi-stage switch fabric can collectively define a single logical entity. A first edge device from the edge devices can be configured to be coupled to a first peripheral processing device from the peripheral processing devices. The second edge device from the edge devices can be configured to be coupled to a second peripheral processing device from the peripheral processing devices. The first edge device can be configured such that virtual resources including a first virtual resource can be defined at the first peripheral processing device. A network management module coupled to the edge devices and configured to provision the virtual resources such that the first virtual resource can be migrated from the first peripheral processing device to the second peripheral processing device.

Abstract: In one embodiment, an apparatus includes a switch core that has a multi-stage switch fabric. A first set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have a protocol. Each peripheral processing device from the first set of peripheral processing devices is a storage node that has virtualized resources. The virtualized resources of the first set of peripheral processing devices collectively define a virtual storage resource interconnected by the switch core. A second set of peripheral processing devices coupled to the multi-stage switch fabric by a set of connections that have the protocol. Each peripheral processing device from the first set of peripheral processing devices is a compute node that has virtualized resources. The virtualized resources of the second set of peripheral processing devices collectively define a virtual compute resource interconnected by the switch core.

Abstract: In one embodiment, an apparatus can include a first edge device that can have a packet processing module. The first edge device can be configured to receive a packet. The packet processing module of the first edge device can be configured to produce cells based on the packet. A second edge device can have a packet processing module configured to reassemble the packet based on the cells. A multi-stage switch fabric can be coupled to the first edge device and the second edge device. The multi-stage switch fabric can define a single logical entity. The multi-stage switch fabric can have switch modules. Each switch module from the switch modules can have a shared memory device. The multi-stage switch fabric can be configured to switch the cells so that the cells are sent to the second edge device.

Abstract: In one embodiment, an apparatus includes a switch core that defines a single logical entity and has a multi-stage switch fabric that has a set of stages physically distributed across a set of chassis. The set of stages collectively has a set of ingress ports and a set of egress ports. The switch core can be configured to be coupled to a set of peripheral processing devices via the set of ingress ports and the set of egress ports. The switch core can be configured to admit a set of cells associated with a packet into an ingress port from the set of ingress ports when delivery of the set of cells can be substantially guaranteed without loss through the multi-stage switch fabric.

Abstract: A front-to-back cooling system allows cooling of an apparatus containing two orthogonal sets of modules. Each set of modules is independently cooled. A vertical set of modules is cooled with vertical air flow across the modules that enters from a front of the apparatus and exhausts from a back of the apparatus. A horizontal set of modules is cooled with horizontal front-to-back air flow. When the horizontal set of modules is at the front of the apparatus, a plenum extending exterior to the vertical set of modules allows exhausting horizontally flowing air to the rear of the apparatus. When the horizontal set of modules is at the rear of the apparatus, a plenum extending exterior to the vertical set of modules allows moving air from the front of the apparatus to a chamber holding the horizontal modules.

Abstract: A network device may include logic configured to receive a packet from a packet forwarding engine, create a flow ID for the packet, determine whether the flow ID matches one of a plurality of flow IDs in a table, determine whether the packet is associated with a flow to be sampled, sample the packet and additional packets associated with the flow that are received from the packet forwarding engine when the flow is to be sampled and transmit the flow ID and the sampled packets via a switch to an interface.

Abstract: Reversible airflow in cooling systems of electronic devices is described. For example, an electronic device may include a reversible fan tray. The fan tray may include symmetric mounting features that allow the fan tray to be mounted in the electronic device in more than one orientation at the same location within the electronic device such that one or more fans in the fan tray either direct air into the electronic device or to pull air from electronic device. The fan tray may further include a symmetric arrangement of connectors that coincide with the symmetric arrangement of mounting features to allow the fan tray to be connected to a power source of the electronic device any of the more than one orientations. An arrangement of electronic devices including reversible fan trays may be configured so that inlet and outlet airflows are separated to increase cooling efficiency of the electronic devices.

Abstract: A two stage rate shaping and scheduling system and method is implemented to control the flow of traffic to at least one output interface. The system and method involves initially queuing incoming packets into type-specific queues and applying individual rate shaping rules to each queue. A first stage arbitration is performed to determine how traffic is queued from the type-specific queues to interface-specific queues. Packets that win arbitration and pass the applied rate shaping rules are queued in interface-specific queues. Rate shaping rules are applied to the interface-specific queues. The interface-specific queues are further distinguished by priority and priority-specific and interface-specific rate shaping rules are applied to each queue. A second stage arbitration is performed to determine how different priority traffic that is targeting the same output interface is dequeued in response to interface-specific requests.

Abstract: A high-speed parallel interface for communicating data between integrated circuits is disclosed. The interface is implemented by a transmitter and receiver pair and a single-ended parallel interconnect bus coupling to the transmitter and receiver pair. As opposed to transmitting small swing signals over differential signal lines, the transmitter transmits data to the receiver at full swing over the single-ended parallel interconnect bus. The invention can be implemented with simple CMOS circuitry that does not consume large die area. Accordingly, many link interfaces can be implemented on a single chip to provide a large data bandwidth.