Abstract: A high-speed parallel interface for communicating data between integrated circuits is disclosed. In one embodiment, the transmitter controller accepts 40-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 40-bit wide data every 167 Mhz clock cycle, and the interconnect bus transmits 10-bit wide data at every transition of a 333 Mhz clock cycle. In another embodiment, the transmitter controller accepts 32-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 32-bit wide data every 167 Mhz clock cycle, and the interconnect bus of this embodiment transmits 8-bit wide data at every transition of a 333 Mhz clock cycle. Output pins of the transmitter interface can be connected to any input pins of the receiver interface. Furthermore, the high-speed parallel interface does not require a fixed phase relationship between the receiver's internal clock(s) and the bus clock signal.

Abstract: A high-speed parallel interface for communicating data between integrated circuits is disclosed. In one embodiment, the transmitter controller accepts 40-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 40-bit wide data every 167 Mhz clock cycle, and the interconnect bus transmits 10-bit wide data at every transition of a 333 Mhz clock cycle. In another embodiment, the transmitter controller accepts 32-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 32-bit wide data every 167 Mhz clock cycle, and the interconnect bus of this embodiment transmits 8-bit wide data at every transition of a 333 Mhz clock cycle. Output pins of the transmitter interface can be connected to any input pins of the receiver interface. Furthermore, the high-speed parallel interface does not require a fixed phase relationship between the receiver's internal clock(s) and the bus clock signal.

Abstract: A high-speed parallel interface for communicating data between integrated circuits is disclosed. The interface is implemented by a transmitter and receiver pair and a single- ended parallel interconnect bus coupling to the transmitter and receiver pair. As opposed to transmitting small swing signals over differential signal lines, the transmitter transmits data to the receiver at full swing over the single-ended parallel interconnect bus. The invention can be implemented with simple CMOS circuitry that does not consume large die area. Accordingly, many link interfaces can be implemented on a single chip to provide a large data bandwidth.

Abstract: A two stage rate shaping and scheduling system and method is implemented to control the flow of traffic to at least one output interface. The system and method involves initially queuing incoming packets into type-specific queues and applying individual rate shaping rules to each queue. A first stage arbitration is performed to determine how traffic is queued from the type-specific queues to interface-specific queues. Packets that win arbitration and pass the applied rate shaping rules are queued in interface-specific queues. Rate shaping rules are applied to the interface-specific queues. The interface-specific queues are further distinguished by priority and priority-specific and interface-specific rate shaping rules are applied to each queue. A second stage arbitration is performed to determine how different priority traffic that is targeting the same output interface is dequeued in response to interface-specific requests.

Abstract: An input-buffered multipoint switch having input channels and output channels includes multilevel request buffers, a data path multiplexer, and a scheduler. The switch has a distinct multilevel request buffer associated with each input channel and each request buffer has multiple request registers of a different request buffer priority. The request registers store data cell transfer requests that have been assigned quality of service (QoS) priorities, where the QoS priorities are related to packet source, destination, and/or application type. The multilevel request registers are linked in parallel to the scheduler to allow arbitration among requests of different input channels and different request buffer priority levels. The preferred arbitration process involves generating QoS priority-specific masks that reflect the output channels required by higher QoS priority requests and arbitrating among requests of the same QoS priority in QoS priority-specific multilevel schedulers.

Abstract: The present invention provides an electronic system which includes an integrated circuit chip having a processor, a memory controller and a bus interface. The bus interface is both a memory interface and a system interface and has at least one address pin line, at least one data transfer pin line and at least one control pin line and is coupled to the processor and the memory controller. An S-DRAM is coupled to the bus interface wherein the processor and the S-DRAM share the same address pin line and data transfer pin line reducing the number of pins necessary to interface with the system. A system interface bridge chip interconnects the bus interface to one or more peripheral devices and includes a protocol module for managing interactions on the bus interface between the processor, the S-DRAM and the system interface bridge chip. An electronic system is thus provided which reduces the number of pins that an integrated circuit chip needs for interfacing without reducing performance.

Abstract: A method and apparatus for forwarding variable-length packets between channel-specific packet processor in a crossbar of a multiport switch involve segmenting variable-length packets into fixed-length payload segments and multiplexing the payload segments with response or request data to form fixed-length switching blocks. The fixed-length switching blocks are transferred to and from the crossbar over respective input and output connections in order to minimize the number of connections between the packet processors and the crossbar. The input and output connections enable the transfer of a current packet through the crossbar while supplying the crossbar with request information necessary to schedule subsequent packets through the crossbar. In a preferred embodiment of the invention, packets are timed to pass through the crossbar one after another in order to utilize the maximum bandwidth of the crossbar.

Abstract: An input-buffered multipoint switch having input channels and output channels includes multi-level request buffers, a data path multiplexer, and a scheduler. The switch has a distinct multi-level request buffer associated with each input channel and each request buffer has multiple request registers for storing data cell transfer requests of different priorities. The multi-level request registers are linked in parallel to the scheduler to allow arbitration among requests of different input channels and different priority levels. The preferred arbitration process involves generating masks that reflect the output channels required by the same priority level requests. Utilizing masks to arbitrate between multiple requests in an input-buffered switch reduces arbitration cycle time and minimizes HOL blocking.

Abstract: A CPU includes a common bus, a bus interface unit (BIU), and a plurality of module units. The BIU includes a decode stage, an arbitration stage, and a control stage. Incoming requests asserted by the CPU module unit are provided to the BIU decode stage which, in response thereto, determines the type of transaction requested, the initiator module unit, and the target module unit. If the target identified in the decoded request is ready to accept a command, the decode stage forwards the request to the arbitration stage. The arbitration stage arbritrates amoung the present requests asserted by the module units and, in response thereto, alerts the control stage as to which of the module units has won the arbitration. The control stage decodes the request corresponding to the module unit that won the arbitration to determine the transaction type and target unit.

Abstract: Requests from CPU module units are arbitrated according to a two-level priority scheme, the first level being of a higher priority than the second level. The first level includes a specific CPU module unit, and the second level includes a predetermined sequence of values corresponding to the remaining CPU module units. During each arbitration cycle, a request from the first level CPU module is automatically granted. If the first level CPU module unit has not asserted a request, requests from the second level module units are arbitrated according to the above-mentioned predetermined sequence. The sequence value corresponding to the second level CPU module whose request was most recently granted is latched. Arbitration is then granted to the module unit corresponding to the sequence value which follows the latched value.

Abstract: A CPU of a microprocessor includes a common bus, a bus interface unit (BIU), and a plurality of module units. The BIU has a plurality of first ports coupled to respective first ports of the module units via dedicated buses therebetween and has a second port coupled to a first port of the common bus. The module units each include a second port coupled to respective second ports of the common bus. Communication between the module units is routed through and controlled by the BIU. To request a transaction, a module unit (the initiator) sends a request to the BIU via its dedicated bus to the BIU. The BIU arbitrates among present requests and, in response thereto, grants the arbitration winner's request and transmits a command to the target of the requested transaction. Preferably, both of these signals being are transmitted via the dedicated buses. Thereafter, data is routed from, for instance, the target, to the BIU via a corresponding dedicated bus.

Abstract: A computer system includes a data processor, a primary translation lookaside buffer for storing page table entries and translating virtual addresses into physical addresses, local memory coupled to the data processor for storing data and computer programs at specified physical addresses, and remotely located memory coupled to the data processor by a computer network for storing data at specified remote physical addresses. The computer system further includes a remote translation lookaside buffer (RTLB) that stores a plurality of remote page table entries. Each remote page table entry represents a mapping between a range of physical addresses and a corresponding range of remote physical addresses. The primary translation lookaside buffer translates a virtual address asserted by the data processor into a physical address.

Abstract: An electronic device and method for utilizing two extra microcode instructions to generate a set of test patterns which provide complete bitwise self-testing of the on-chip memory of a microcode sequencer. The self-testing sequence can be triggered by a single external interface event.

Abstract: An electronic device and method for utilizing two extra microcode instructions to generate a set of test patterns which provide complete bitwise self-testing of the on-chip memory of a microcode sequencer. The self-testing sequence can be triggered by a single external interface event.