Abstract: A method of sending data is provided. The method may include, executed in a master, applying a first code to an address of an addressed data sink of a slave, thereby forming a master-encoded address, combining the data with the master-encoded address using a reversible function, thereby forming a data-address-combination, and sending the data-address-combination and the address from the master to the slave.

Abstract: A method of sending data is provided. The method may include, executed in a master, applying a first code to an address of an addressed data sink of a slave, thereby forming a master-encoded address, combining the data with the master-encoded address using a reversible function, thereby forming a data-address-combination, and sending the data-address-combination and the address from the master to the slave.

Abstract: In accordance with one embodiment, a method for accessing a memory is provided, including carrying out a first access to the memory and charging, for a memory cell, a bit line coupled to the memory cell to a value which is stored or to be stored in the memory cell, holding the state of the bit line until a second access, which follows the first access, and outputting the held state if the second access is a read access to the memory cell.

Abstract: The disclosure includes embodiments that apply to an interconnect architecture having multiple system masters and at least one shared resource. The disclosure provides a system and method for providing synchronization for transactions in a multi-master interconnect architecture that employs at least one shared resource, or slave component.

Abstract: In accordance with one embodiment, a method for accessing a memory is provided, including carrying out a first access to the memory and charging, for a memory cell, a bit line coupled to the memory cell to a value which is stored or to be stored in the memory cell, holding the state of the bit line until a second access, which follows the first access, and outputting the held state if the second access is a read access to the memory cell.

Abstract: An apparatus is provided comprising at least two processing entities. Shared resources are usable by a first and a second processing entity. A use of the shared resources is detected, and the execution of instructions associated with said processing entities is controlled based on the detection.

Abstract: A system, having a stream cache and a storage. The stream cache includes a stream cache controller adapted to control or mediate input data transmitted through the stream cache; and a stream cache memory. The stream cache memory is adapted to both store at least first portions of the input data, as determined by the stream cache controller, and to further output the stored first portions of the input data to a processor. The storage is adapted to receive and store second portions of the input data, as determined by the stream cache controller, and to further transmit the stored second portions of the input data for output to the processor.

Abstract: An apparatus is provided comprising at least two processing entities. Shared resources are usable by a first and a second processing entity. A use of the shared resources is detected, and the execution of instructions associated with said processing entities is controlled based on the detection.

Abstract: Methods and apparatuses for processing data are provided. In one embodiment, a data processing operation which is assigned a predefined maximum duration is started. The progress of the data processing operation is checked at a predefined point in time and a priority of the data processing operation is changed on the basis of the progress of the data processing operation.

Abstract: A data processing device includes at least one first and one second component which are coupled to one another. The first component is operable in a first endian mode, while the second component is operable in a second endian mode, which is different from the first endian mode.

Abstract: A data transmission device forwards data that have been received from a first device, intended for a second device, to the second device. The data transmission device is distinguished in that it has connections for connecting at least two data buses and can output data received by a first data bus either onto the same data bus or onto another data bus immediately or later. Therefore, the data transmission device can be used selectively, alternately or simultaneously as a DMA controller and a bus bridge. It also has additional functions unrelated to DMA controllers and bus bridges.

Abstract: In the case of devices with a program-controlled circuit arrangement operating program instructions are necessary for their operation. In order to reduce the storage space necessary for this, in the case of devices which have a connection to a data transmission network in any case, the operating program instructions are not held in the device, but loaded via the data transmission network. For this purpose the circuit arrangement has a start procedure memory, in which is stored a start procedure set up in such a way that for its execution a processor unit connects up via the data transmission network by means of the interface to an operating program server and from this loads operating program instructions into a main memory connected to the processor unit.

Abstract: A method and device for the uniform output of asynchronously transmitted digital values is provided, including: receiving the digital values in a receiver from a transmission path; outputting the digital values from the receiver on the basis of an output clock for further processing; transmitting the digital values to the transmission path by a transmission device of the receiver, determining the amount of the digital values received by the receiver in relation to the time; adjusting the output clock on the basis of the determined amount in such a way that the digital values are outputted at the frequency with which on time average the receiver receives the digital values; and adjusting a transmission clock of the transmission device to correspond to the output clock of the receiver.

Abstract: A program-controlled unit includes a selection device which can determine whether the program-controlled unit is to be emulated by using a first emulation unit or by using a second emulation unit. As a result, it is possible to provide a mass production version of the program-controlled unit with an emulation unit having a reduced functional and/or performance scope. Therefore, an emulatable mass production version of the program-controlled unit can be made available which is only insignificantly more expensive, if at all, than a non-emulatable version.

Abstract: A method for transferring data between a first device and a second device is provided. In the method an address identifying the second device is output by the first device or an address generating device connected downstream thereof. An association between the address and the device addressed as a result, and/or the data that are to be transferred are manipulated, during the transfer, in dependence on the outputted address.

Abstract: A DSL communication apparatus with lifeline functionality is provided, the DSL communication apparatus (3) in particular being suitable for CVoDSL (“Channelized Voice over Digital Subscriber Line”) transmission. The DSL communication apparatus (3) comprises a central processing unit (11) which detects a local power failure state of a local power supply unit (23) being associated with the DSL communication apparatus (3). In this case, the central processing unit (11) changes the operation of the DSL communication apparatus (3) from a normal operation mode to an intermediate operation mode, generates an interrupt for stopping a voice coprocessor unit (8), initializes a download of a lifeline operation firmware from a FLASH memory (12) to the voice coprocessor unit (8), and then starts a new initialization of the voice coprocessor unit (8).

Abstract: The memory device, for the purpose of serial data transfer of binary data, is arranged between at least two subscribers of a data transmission system. The memory is divided into a multiplicity of memory objects, which are typically of the same size and some of which are organized to form FIFO structures. The FIFO structures are used to buffer the typically asynchronous access operations between the subscribers at different data transmission rates and with a certain data depth, and to thereby decouple them from one another. The data transfer is largely under data control and thus requires minimal computation complexity in a central processing unit. The memory objects of the memory can advantageously be operated flexibly and independently of one another, in four different operating modes.

Abstract: In the case of devices with a program-controlled circuit arrangement operating program instructions are necessary for their operation. In order to reduce the storage space necessary for this, in the case of devices which have a connection (6) to a data transmission network (7) in any case, the operating program instructions are not held in the device, but loaded via the data transmission network (7). For this purpose the circuit arrangement (1) has a start procedure memory (3), in which is stored a start procedure set up in such a way that for its execution a processor unit (2) connects up via the data transmission network (7) by means of the interface (6) to an operating program server and from this loads operating program instructions into a main memory (5) connected to the processor unit (2).

Abstract: The disclosed A/D conversion system is designed to signal the beginning or the impending beginning of an A/D conversion and/or to request the implementation of an A/D conversion from another A/D converter. As a result, it is possible to have a plurality of A/D converters work absolutely time-synchronously with minimal outlay.

Abstract: An DSL communication apparatus with lifeline functionality is provided, the DSL coomunication apparatus (3) in particular being suitable for CVoDSL (“Channelized Voice over Digital Subscriber Line”) transmission. The DSL communication apparatus (3) comprises a central processing unit (11) which detects a local power failure state of a local power supply unit (23) being associated with the DSL communication apparatus (3). In this case, the central processing unit (11) changes the operation of the DSL communication apparatus (3) from a normal operation mode to an intermediate operation mode, generates an interrupt for stopping a voice coprocessor unit (8), initializes a download of a lifeline operation firmware from a FLASH memory (12) to the voice coprocessor unit (8), and then starts a new initialization of the voice coprocessor unit (8).