Abstract: With regard to the asynchronous transmission of digital values between a transmitter, from which the digital values are transmitted at a first frequency and a receiver (A, B), in which the received digital values are further processed and in particular outputted at a second frequency, it is never possible to harmonize the first frequency with the second frequency. In consequence as a result of frequency differences never to be harmonized an overflow or under-run of the transmitted digital values occurs.

Abstract: An A/D converter arrangement comprises an A/D converter (6) to which analog signals from a plurality of signal channels (2) can be fed for A/D conversion. With the help of an appropriate control means (8), converter parameters of the A/D converter (6) or even other operating parameters of the A/D converter arrangement, such as certain functions performed in response to an A/D conversion which has been carried out for example, are set in a channel-specific way as a function of the signal channel (2) which is to be converted at the time.

Abstract: A data transmission device forwards data that have been received from a first device, intended for a second device, to the second device. The data transmission device is distinguished in that it has connections for connecting at least two data buses and can output data received by a first data bus either onto the same data bus or onto another data bus immediately or later. Therefore, the data transmission device can be used selectively, alternately or simultaneously as a DMA controller and a bus bridge. It also has additional functions unrelated to DMA controllers and bus bridges.

Abstract: A method for A/D conversion of analog signals using an A/D converter, and to an appropriate A/D converter circuit. In order to process converter request signals from different converter request sources requesting analog signals for conversion, the invention proposes assigning definable, selectable priorities to the different converter request sources. If there is a request for A/D conversion from a converter request source, the system establishes which of the converter request sources requesting A/D conversion has the highest priority. An analog signal from this selected converter request source is then supplied to the A/D converter.

Abstract: A program-controlled unit includes a selection device which can determine whether the program-controlled unit is to be emulated by using a first emulation unit or by using a second emulation unit. As a result, it is possible to provide a mass production version of the program-controlled unit with an emulation unit having a reduced functional and/or performance scope. Therefore, an emulatable mass production version of the program-controlled unit can be made available which is only insignificantly more expensive, if at all, than a non-emulatable version.

Abstract: A program-controlled unit is described and is distinguished in that it has a connection which can be used to signal to it whether it is connected to a particular other circuit, and/or in that the program-controlled unit has a connection which it can use to signal to an external device that it is currently communicating or cooperating with a particular other device. Such a program-controlled unit can communicate and cooperate with devices connected to it better than has been the case to date, but at the same time can operate correctly under all circumstances even without these devices.

Abstract: The buffer memory configuration has a memory disposed between a USB and a central processing unit. The memory can be mapped onto an address space which is exactly half as large as the memory itself. The first half of the memory defines a first memory page and the second half of the memory defines a second memory page, and each address in the address space is assigned exactly one memory location on each of the memory pages. A memory management unit generates a first significant bit which assigns in each case the two memory locations having the same address to the address space of the first memory page and to the address space of the second memory page. The buffer memory architecture enables the memory independently to manage the data to be transferred. The two memory pages serve to decouple the central processing unit CPU and the bus. Both memory pages are virtually visible to the user but only one of the memory pages can ever be addressed for data transfer.

Abstract: An interface is connected between a bus system and a unit which is to respond through the bus system. The interface is constructed for the simultaneous connection of different types of bus systems. As a result, the interface can cooperate optimally with the units that use it, even when it is used, or is to be capable of being used, by a plurality of units.

Abstract: The method is distinguished by the fact that an address, which is output by the first device or an address generating device connected downstream thereof, for determining the second device, and/or the association between the address and the device addressed as a result, and/or the data that are to be transferred are manipulated, during the transfer, in dependence on the address output by the first device or the address generating device connected downstream thereof.

Abstract: The bridge module is connected between at least two bus systems and is suitable for serial data transfer of binary data from one of the bus systems to the other one of the bus systems. A single memory device is provided for buffer storage of the data during a data transfer. The data transfer, which is controlled exclusively by the data to be transmitted, is thus carried out in a simple manner and completely automatically, without the interposition of a processor unit. It is thereby possible very easily and thus also at an attractive cost to specify a module which is suitable for the data transfer between different bus systems.

Abstract: A timer for an A/D converter generates a request signal for A/D conversion by the A/D converter. In addition to the usual request signal, the timer produces a further signal which is used, before one cycle of the timer has elapsed, to block the A/D converter for low-priority requests from other requesting devices and to reserve it for the timer. In this manner, the signal to be converted from the timer can be sampled at reproducible, equidistant instants without having to wait for the end of the last conversion.