Abstract: An antifuse apparatus includes first and second independent current paths connected to an antifuse. One of the current paths can be used to program the antifuse, and the other current path can be used to detect the status (programmed or not programmed) of the antifuse.

Abstract: A memory device is provided, the memory device having a memory cell, a programming unit for programming the memory cell, and a switching unit for optionally connecting or isolating a terminal of the memory cell to or from a potential which serves for altering an electrical property of the memory cell and for thereby effecting an altered programming state of the memory cell.

Abstract: A read-out circuit is disclosed, where the circuit reads information out of a memory unit comprising two non-volatile memory cells (F2, F3). The cells have different programming states, and the memory information of the memory unit is given by the programming states of the two memory cells (F2, F3). The read-out circuit has a volatile signal memory (INV4, INV5), the inputs of which are connected to the read outputs of the memory cells (F2, F3).

Abstract: A semiconductor device is provided which is formed of a wafer having on a surface thereof an area efficient arrangement of at least two antifuses in vertically stacked relation and sharing a common intermediate electrode therebetween. The arrangement includes at least one lower antifuse having a lower counter electrode and a lower fusible insulator portion defining a lower fuse element of an initial high electrical resistance state which interconnects the lower counter electrode with the common intermediate electrode, and at least one upper antifuse, which may be the same as or different from the lower antifuse, the upper antifuse having an upper counter electrode and an upper fusible insulator portion defining an upper fuse element of an initial high electrical resistance state which interconnects the upper counter electrode with the common intermediate electrode.

Abstract: It is proposed that bitline inversion coding data be integrally stored in the structure of a column multiplexer of a storage device. For this purpose, connections to a predefined potential are selectively provided at connection points, which are respectively assigned to one of the bitlines connected to the column multiplexer, in dependence on whether or not the assignment of a first state and of a second state of memory cells, connected to the bitline, to a binary value “0” and to a binary value “1” is inverted for the respective bitline. The connection points are connected to a common nodal point via switching means. The switching means are activated through control signals of the column multiplexer. Selection signals for activating inverter means, in order to effect a selective inversion of values read out from the memory cells, are generated in dependence on the signal level at the common nodal point.

Abstract: A memory apparatus is configured by obtaining test information for each of group of memory locations within the memory apparatus, compressing the test information to produced compressed test information and, based on the compressed test information, replacing a group of redundant memory circuits respectively associated with the group of memory locations.

Abstract: Described are integrated circuit chips that are capable of self-adjusting an internal voltage of the integrated circuit chip and methods for adjusting the internal voltage of an integrated circuit chip. The methods include comparing an internally generated voltage to an external target voltage.

Abstract: A multiple trip point fuse latch device and method is disclosed. Multiple read inputs to a fuse latch enable the altering of the resistive trip point of the fuse latch. A multiple trip point fuse latch may be combined with a slave latch to form a master-slave flip-flop, and multiple master-slave flip-flops may be connected in series to form a shift register. Changing the trip point permits the use of a test procedure that may analyze the margins of a fuse latch during the fuse read operation.

Abstract: A system and method is provided for controlling the impedance and current of an off chip driver circuit to match to load driven by the driver and for reducing noise and ringing in the off chip driver circuit. The driver comprises a pull up transistor for switching the output of the driver to a high-voltage, a pull down transistor for switching the output of the driver to a low voltage, a first current mirror transistor coupled to the pull up transistor for controlling the current transmitted to a load connected to the driver when the output of the driver is at the high-voltage, and a second current mirror transistor coupled to the pull down transistor for controlling the current transmitted to the load when the output of the driver is at the low voltage. In addition, the driver may include a first pre-driver providing a gate signal for the pull up transistor having a controlled slew rate and a second pre-driver providing a gate signal for the pull down transistor having a controlled slew rate.

Abstract: A semiconductor device is provided which is formed of a wafer having on a surface thereof an area efficient arrangement of at least two antifuses in vertically stacked relation and sharing a common intermediate electrode therebetween. The arrangement includes at least one lower antifuse having a lower counter electrode and a lower fusible insulator portion defining a lower fuse element of an initial high electrical resistance state which interconnects the lower counter electrode with the common intermediate electrode, and at least one upper antifuse, which may be the same as or different from the lower antifuse, the upper antifuse having an upper counter electrode and an upper fusible insulator portion defining an upper fuse element of an initial high electrical resistance state which interconnects the upper counter electrode with the common intermediate electrode.

Abstract: Address information representing failed elements in an array portion of a device is delivered. Respective fail address bit values are stored in a plurality of fuses. A signal associated with a respective value of a portion of a further address is received. When the signal is received, one of the fail address bit values is delivered from one of the fuses to a corresponding latch circuit. The latch circuit receives fail address bit values from at least two of the fuses. One of the fail address bit values is selected based on the value associated with the signal. The latch circuit is activated to deliver the fail address bit value.

Abstract: A sequential fuse latch device comprises a plurality of fuse latches, wherein each fuse latch is a data storage element, and a shift register comprising a plurality of pointer latches, wherein each pointer latch is connected to at least one fuse latch, wherein the shift register controls a sequential operation of the plurality of fuse latches.

Abstract: Described are integrated circuit chips that are capable of self-adjusting an internal voltage of the integrated circuit chip and methods for adjusting the internal voltage of an integrated circuit chip. The methods include comparing an internally generated voltage to an external target voltage.

Abstract: Address information representing failed elements in an array portion of a device is delivered. Respective fail address bit values are stored in a plurality of fuses. A signal associated with a respective value of a portion of a further address is received. When the signal is received, one of the fail address bit values is delivered from one of the fuses to a corresponding latch circuit. The latch circuit receives fail address bit values from at least two of the fuses. One of the fail address bit values is selected based on the value associated with the signal. The latch circuit is activated to deliver the fail address bit value.

Abstract: An antifuse apparatus includes first and second independent current paths connected to an antifuse. One of the current paths can be used to program the antifuse, and the other current path can be used to detect the status (programmed or not programmed) of the antifuse.

Abstract: A multiple trip point fuse latch device and method is disclosed. Multiple read inputs to a fuse latch enable the altering of the resistive trip point of the fuse latch. A multiple trip point fuse latch may be combined with a slave latch to form a master-slave flip-flop, and multiple master-slave flip-flops may be connected in series to form a shift register. Changing the trip point permits the use of a test procedure that may analyze the margins of a fuse latch during the fuse read operation.

Abstract: A sequential fuse latch device comprises a plurality of fuse latches, wherein each fuse latch is a data storage element, and a shift register comprising a plurality of pointer latches, wherein each pointer latch is connected to at least one fuse latch, wherein the shift register controls a sequential operation of the plurality of fuse latches.

Abstract: A semiconductor dynamic random access memory (DRAM) 300 with a programmable memory refresh counter 345 is presented. The counter 345 permits the specification of portions of the DRAM 300 to be refreshed, saving power and time over DRAMs that refresh the entire memory. The counter 345 may be programmed with a wordline address at the beginning of a block of memory and subsequent refresh operations automatically increment or decrement the value in the counter. Additionally, blocks of the memory not being refreshed can be accessed (written or read), improving the utilization of the memory device.

Abstract: A precharge command can be issued to a single bank or a precharge-all command can be issued to all banks of an integrated circuit memory device (e.g., DRAM circuit) at any time during normal operation of the device. Internal circuits are provided to decode the respective commands and send them to the different independent memory banks of the integrated circuit memory device. A local precharge control unit (or circuit) is present inside each of the memory banks that can receive and process the decoded precharge commands. If certain specified timing conditions are met, the local precharge control unit can issue and store a precharge request for a specific bank. The precharge request can be held back until all timing requirements are fulfilled. The precharge request can then be automatically executed.

Abstract: A semiconductor dynamic random access memory (DRAM) 300 with a programmable memory refresh counter 345 is presented. The counter 345 permits the specification of portions of the DRAM 300 to be refreshed, saving power and time over DRAMs that refresh the entire memory. The counter 345 may be programmed with a wordline address at the beginning of a block of memory and subsequent refresh operations automatically increment or decrement the value in the counter. Additionally, blocks of the memory not being refreshed can be accessed (written or read), improving the utilization of the memory device.