Patents by Inventor Hag-ju Cho
Hag-ju Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230402382Abstract: A semiconductor device includes: a base substrate; a first interlayer insulating layer disposed on the base substrate; a power rail disposed inside the first interlayer insulating layer; an active pattern extended in a first horizontal direction and disposed on the first interlayer insulating layer; a gate electrode extended in a second horizontal direction different from the first horizontal direction and disposed on the active pattern; a gate cut extended in the first horizontal direction and disposed on the power rail, wherein the gate cut separates the gate electrode; and a power rail via disposed inside the gate cut, wherein the power rail via is overlapped by the power rail.Type: ApplicationFiled: February 24, 2023Publication date: December 14, 2023Inventors: Jin Kyu KIM, Yun Suk NAM, Kyoung Woo LEE, Ho-Jun KIM, Da Rong OH, Sung Moon LEE, Hag Ju CHO, Seung Min CHA
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Patent number: 11024631Abstract: An integrated circuit device includes a static random access memory (SRAM) array, and the SRAM array includes first to fourth active fins extending parallel to each other in a first direction, a first gate line overlapping the second to fourth active fins, a second gate line spaced apart from the first gate line in the first direction and overlapping the first to third active fins, a third gate line spaced apart from the first gate line in the first direction and overlapping the fourth active fin, a fourth gate line spaced apart from the second gate line in the first direction and overlapping the first active fin, a first field isolation layer contacting one end of the second active fin, and a second field isolation layer contacting one end of the third active fin. The first to fourth gate lines extend in a second direction intersecting the first direction.Type: GrantFiled: July 8, 2019Date of Patent: June 1, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won Cheol Jeong, Hag Ju Cho
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Publication number: 20200227421Abstract: An integrated circuit device includes a static random access memory (SRAM) array, and the SRAM array includes first to fourth active fins extending parallel to each other in a first direction, a first gate line overlapping the second to fourth active fins, a second gate line spaced apart from the first gate line in the first direction and overlapping the first to third active fins, a third gate line spaced apart from the first gate line in the first direction and overlapping the fourth active fin, a fourth gate line spaced apart from the second gate line in the first direction and overlapping the first active fin, a first field isolation layer contacting one end of the second active fin, and a second field isolation layer contacting one end of the third active fin. The first to fourth gate lines extend in a second direction intersecting the first direction.Type: ApplicationFiled: July 8, 2019Publication date: July 16, 2020Inventors: WON CHEOL JEONG, Hag Ju Cho
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Publication number: 20160276342Abstract: Semiconductor devices including STI liners are provided. The semiconductor devices may include a STI trench that defines an active region in a substrate, a STI liner that extends conformally along side walls and a bottom surface of the STI trench, a device isolation film that is on the STI liner and fills up at least a part of the STI trench, a first gate structure that is disposed on the active region, and a second gate structure that is spaced apart from the first gate structure. The second gate structure may include a gate insulating film contacting the device isolation film, a gate electrode on the gate insulating film, and spacers on both sides of the gate electrode. Lower surfaces of the spacers may contact an upper surface of the STI liner.Type: ApplicationFiled: January 5, 2016Publication date: September 22, 2016Inventors: Sun-Me LIM, Young-Dal LIM, Hag-Ju CHO
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Patent number: 9236313Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.Type: GrantFiled: December 8, 2014Date of Patent: January 12, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Hoon-joo Na, Yu-gyun Shin, Hong-bae Park, Hag-ju Cho, Sug-hun Hong, Sang-jin Hyun, Hyung-seok Hong
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Publication number: 20150093888Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.Type: ApplicationFiled: December 8, 2014Publication date: April 2, 2015Inventors: Hoon-joo Na, Yu-gyun Shin, Hong-bae Park, Hag-ju Cho, Sug-hun Hong, Sang-jin Hyun, Hyung-seok Hong
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Patent number: 8932922Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.Type: GrantFiled: May 26, 2011Date of Patent: January 13, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Hoon-joo Na, Yu-gyun Shin, Hong-bae Park, Hag-ju Cho, Sug-hun Hong, Sang-jin Hyun, Hyung-seok Hong
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Patent number: 8748239Abstract: A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer.Type: GrantFiled: August 1, 2013Date of Patent: June 10, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Pil Kim, Young-Goan Jang, Dong-Won Kim, Hag-Ju Cho
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Publication number: 20130316514Abstract: A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer.Type: ApplicationFiled: August 1, 2013Publication date: November 28, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Pil KIM, Young-Goan JANG, Dong-Won KIM, Hag-Ju CHO
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Patent number: 8557651Abstract: In an etchant for etching a capping layer having etching selectivity with respect to a dielectric layer, the capping layer changes compositions of the dielectric layer, to thereby control a threshold voltage of a gate electrode including the dielectric layer. The etchant includes about 0.01 to 3 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt and a solvent. Accordingly, the dielectric layer is prevented from being damaged by the etching process for removing the capping layer and the electric characteristics of the gate electrode are improved.Type: GrantFiled: March 4, 2011Date of Patent: October 15, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hyo-San Lee, Bo-Un Yoon, Kun-Tack Lee, Hag-Ju Cho, Sang-Jin Hyun, Hoon-Joo Na, Hyung-Seok Hong
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Patent number: 8524554Abstract: A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.Type: GrantFiled: October 16, 2012Date of Patent: September 3, 2013Assignees: IMEC, Samsung Electronics Co., Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hag-Ju Cho, Anabela Veloso, HongYu Yu, Stefan Kubicek, Shou-Zen Chang
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Patent number: 8501550Abstract: A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer.Type: GrantFiled: September 21, 2011Date of Patent: August 6, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Pil Kim, Young-Goan Jang, Dong-Won Kim, Hag-Ju Cho
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Patent number: 8367502Abstract: The method involves providing a semiconductor substrate comprising first and second regions in which different conductive metal-oxide semiconductor (MOS) transistors are to be formed. A gate dielectric layer above the semiconductor substrate sequentially forming a first metallic conductive layer and a second metallic conductive layer on and above the gate dielectric layer; covering the second region with a mask, and performing ion plantation of a first material into the first metallic conductive layer of the first region. Removing the second metallic conductive layer of the first region and forming a first gate electrode of the first region and a second gate electrode of the second region by patterning the gate dielectric layer and the first metallic conductive layer of the first region, and the gate dielectric layer, the first metallic conductive layer, and the second metallic conductive layer of the second region.Type: GrantFiled: December 17, 2009Date of Patent: February 5, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-bae Park, Hag-ju Cho, Sug-hun Hong, Sang-jin Hyun, Hoon-joo Nah, Hyung-seok Hong
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Patent number: 8313993Abstract: A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.Type: GrantFiled: January 22, 2009Date of Patent: November 20, 2012Assignees: IMEC, Samsung Electronics Co., Ltd., Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hag-Ju Cho, Anabela Veloso, HongYu Yu, Stefan Kubicek, Shou-Zen Chang
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Patent number: 8293599Abstract: A semiconductor device that has a dual gate having different work functions is simply formed by using a selective nitridation. A gate insulating layer is formed on a semiconductor substrate including a first region and a second region, on which devices having different threshold voltages are to be formed. A diffusion inhibiting material is selectively injected into the gate insulating layer in one of the first region and the second region. A diffusion layer is formed on the gate insulating layer. A work function controlling material is directly diffused from the diffusion layer to the gate insulating layer using a heat treatment, wherein the gate insulting layer is self-aligned capped with the selectively injected diffusion inhibiting material so that the work function controlling material is diffused into the other of the first region and the second region. The gate insulating layer is entirely exposed by removing the diffusion layer. A gate electrode layer is formed on the exposed gate insulating layer.Type: GrantFiled: August 12, 2009Date of Patent: October 23, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hoon-joo Na, Yu-gyun Shin, Hong-bae Park, Hag-ju Cho, Sug-hun Hong, Sang-jin Hyun, Hyung-seok Hong
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Publication number: 20120238067Abstract: Methods of fabricating semiconductor devices including providing a substrate having a channel region defined therein; forming an insulation layer on the substrate; forming a gate trench for forming a gate electrode having a sidewall portion, a bottom portion and an edge portion between the sidewall portion and the bottom portion on the insulation layer, the gate electrode trench overlapping the channel region; and forming a gate electrode in the gate electrode trench. Forming the gate electrode includes forming a first metal layer pattern in the gate electrode trench and forming a second metal layer pattern on the first metal layer pattern.Type: ApplicationFiled: March 16, 2012Publication date: September 20, 2012Inventors: Won-Cheol Jeong, Yun-Young Yeoh, Dong-Won Kim, Hong-Bae Park, Hag-Ju Cho
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Publication number: 20120115298Abstract: A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer.Type: ApplicationFiled: September 21, 2011Publication date: May 10, 2012Inventors: Jong-Pil KIM, Young-Goan JANG, Dong-Won KIM, Hag-Ju CHO
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Patent number: 8119511Abstract: A non-volatile memory device having a control gate on top of the second dielectric (interpoly or blocking dielectric), at least a bottom layer of the control gate in contact with the second dielectric being constructed in a material having a predefined high work-function and showing a tendency to reduce its work-function when in contact with a group of certain high-k materials after full device fabrication. At least a top layer of the second dielectric, separating the bottom layer of the control gate from the rest of the second dielectric, is constructed in a predetermined high-k material, chosen outside the group for avoiding a reduction in the work-function of the material of the bottom layer of the control gate. In the manufacturing method, the top layer is created in the second dielectric before applying the control gate.Type: GrantFiled: April 5, 2011Date of Patent: February 21, 2012Assignee: IMECInventors: Bogdan Govoreanu, HongYu Yu, Hag-Ju Cho
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Publication number: 20110223758Abstract: A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.Type: ApplicationFiled: May 26, 2011Publication date: September 15, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hoon-joo Na, Yu-gyun Shin, Hong-bae Park, Hag-ju Cho, Sug-hun Hong, Sang-jin Hyun, Hyung-seok Hong
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Publication number: 20110217833Abstract: In an etchant for etching a capping layer having etching selectivity with respect to a dielectric layer, the capping layer changes compositions of the dielectric layer, to thereby control a threshold voltage of a gate electrode including the dielectric layer. The etchant includes about 0.01 to 3 percent by weight of an acid, about 10 to 40 percent by weight of a fluoride salt and a solvent. Accordingly, the dielectric layer is prevented from being damaged by the etching process for removing the capping layer and the electric characteristics of the gate electrode are improved.Type: ApplicationFiled: March 4, 2011Publication date: September 8, 2011Inventors: Hyo-San Lee, Bo-Un Yoon, Kun-Tack Lee, Hag-Ju Cho, Sang-Jin Hyun, Hoon-Joo Na, Hyung-Seok Hong