Abstract: Certain aspects of the present disclosure generally relate to a static random-access memory (SRAM) implemented using both a gate-all-around (GAA)-type transistor and a fin field-effect transistor (FinFET). For example, certain aspects are directed to an SRAM memory cell having a flip-flop (FF) having a pull-up (PU) transistor and a pull-down (PD) transistor, and a pass-gate (PG) transistor coupled between a bit line of the SRAM memory cell and the FF, a gate of the PG transistor being coupled to a word line (WL) of the SRAM memory cell. In certain aspects, at least one of the PU transistor, the PD transistor, or the PG transistor comprises a GAA transistor, and at least another one of the PU transistor, the PD transistor, or the PG transistor comprises a FinFET.

Abstract: Aspects disclosed herein include circuits employing a double diffusion break (DDB) and a single diffusion break (SDB) in different type diffusion regions, and related fabrication methods are disclosed. In exemplary aspects disclosed herein, either a DDB or a SDB is formed in the N-type diffusion region(s) and the opposing type diffusion, either a SDB or DDB, is formed in the P-type diffusion region(s). Forming different diffusion breaks between a DDB and a SDB in different diffusion regions of the circuit can be employed to induce channel strain that will increase carrier mobility of either P-type or N-type semiconductor devices formed in respective P-type or N-type diffusion region(s), while avoiding or reducing such induced channel strain in either P-type or N-type semiconductor devices formed in respective P- or N-type diffusion region(s) that may degrade carrier mobility.

Abstract: Offsetting or modulating the location of a gate between two transistors may achieve a lower power circuit and a higher speed circuit depending on the new location of the gate. In one example, a gate between a PFET transistor and an NFET transistor may be offset towards the PFET transistor to achieve a higher speed circuit than a conventional circuit with the gate located equal distance between the transistors. In another example, a gate between a PFET transistor and an NFET transistor may be offset towards the NFET transistor to achieve a lower power circuit than a conventional circuit with the gate located equal distance between the transistors.

Abstract: In accordance with some embodiments herein, methods of determining signatures of HMGB1 isoforms in a subject are provided. In some embodiments, antibodies that bind specifically to HMGB1 isoforms are provided. In some embodiments, immunoassay kits are provided.

Abstract: A semiconductor device with low parasitic capacitance comprises a substrate. The semiconductor device also comprises a gate region on the substrate. The semiconductor device further comprises a contact region on the substrate, wherein the contact region comprises a first portion and a second portion, wherein the first portion is in contact with the substrate and has a first surface above the substrate, and wherein the second portion is in contact with the substrate and has a second surface above the substrate different from the first surface.

Abstract: A semiconductor device may include a source/drain contact trench adjacent to a gate. The source/drain contact trench may include a first portion and a second portion on the first portion. The semiconductor device also may include an insulating contact spacer liner within the source/drain contact trench. The insulating contact spacer liner contacts the first portion but not the second portion of the source/drain contact trench. The semiconductor device may further include a conductive material within the insulating contact spacer liner and the second portion of the source/drain contact trench. The conductive material may land in a source/drain region of the semiconductor device.

Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for programming a device having one or more programmable circuits to implement, for example, a machine learning model. One example apparatus generally includes a plurality of word lines, a plurality of bit lines, and an array of programmable circuits. Each programmable circuit is coupled to a corresponding word line in the plurality of word lines and to a corresponding bit line in the plurality of bit lines and comprises: a main resistor coupled between the corresponding word line and the corresponding bit line, an auxiliary resistor, a fuse coupled in series with the auxiliary resistor, wherein the auxiliary resistor and the fuse are coupled between the corresponding word line and the corresponding bit line, and a programming circuit configured to selectively blow the fuse.

Abstract: We describe a multimode reconfigurable optical spatial mode multiplexing system having first and second first and second input beams and a beam combiner to combine these into an optical output. At least one of the paths comprises a polarisation-independent reconfigurable phase modulator to impose a controllable phase profile on an input beam in an input beam phase modulating optical path, to controllably convert a spatial mode order of the input beam from a lower to a higher order spatial mode. The system also has a control input to control the phase modulator to configure the phase profile for the mode conversion. The input beams are combined into a multiple spatial mode combined beam output independent of a polarisation of the input beams. The number of spatial modes of the combined beam can be more than a number of spatial modes in either of the first and second input beams separately.

Abstract: We describe a wavelength division multiplexed (WDM) reconfigurable optical switch, the switch comprising: a set of arrays of optical beam connections, each comprising an array of optical outputs and having an optical input to receive a WDM input optical signal; a first diffractive element to demultiplexed said WDM input optical signal into a plurality of demultiplexed optical input beams, and to disperse said demultiplexed optical input beams spatially along a first axis; first relay optics between said set of arrays of optical beam connections and said first diffractive element; and a reconfigurable holographic array comprising a 2D array of reconfigurable sub-holograms defining sub-hologram rows and columns; wherein said arrays of said set of arrays are at least one dimensional arrays extending spatially in a direction parallel to said first axis and arranged in a column defining a second axis orthogonal to said first axis; wherein said sub-hologram rows are aligned along said first axis, and wherein said s

Abstract: Circuits employing asymmetric diffusion breaks in different type semiconductor diffusion regions are disclosed. In examples herein, diffusion breaks having dimensions asymmetric to each other are provided in different types of diffusion regions in a circuit to increase carrier mobility in semiconductor channels of a semiconductor device formed in different diffusion regions. In examples herein, the circuit includes a P-type and N-type semiconductor device(s) formed in a P-type and an N-type diffusion region(s), respectively, formed in the substrate. Complementary metal oxide semiconductor (CMOS) circuits can be realized from the P-type and N-type semiconductor devices. Diffusion breaks can induce strain in the diffusion regions with a magnitude of the induced strain related to a dimension of the diffusion breaks. As one example, an induced tensile strain may increase carrier mobility in N-type devices and decrease carrier mobility in P-type devices, with induced compressive strain having the opposite effect.

Abstract: Aspects of the disclosure are directed to isolation in integrated circuits. In accordance with one aspect, implementing a complementary metal oxide semiconductor (CMOS) isolation in an integrated circuit (IC) includes etching an interlayer dielectric (ILD) between two of a plurality of gates in a first section of an integrated circuit (IC); etching a semiconductor substrate to form a trench within an active region in the first section; and filling the trench with an insulator in the first section and planarizing the integrated circuit (IC).

Abstract: Circuits employing asymmetric diffusion breaks in different type semiconductor diffusion regions are disclosed. In examples herein, diffusion breaks having dimensions asymmetric to each other are provided in different types of diffusion regions in a circuit to increase carrier mobility in semiconductor channels of a semiconductor device formed in different diffusion regions. In examples herein, the circuit includes a P-type and N-type semiconductor device(s) formed in a P-type and an N-type diffusion region(s), respectively, formed in the substrate. Complementary metal oxide semiconductor (CMOS) circuits can be realized from the P-type and N-type semiconductor devices. Diffusion breaks can induce strain in the diffusion regions with a magnitude of the induced strain related to a dimension of the diffusion breaks. As one example, an induced tensile strain may increase carrier mobility in N-type devices and decrease carrier mobility in P-type devices, with induced compressive strain having the opposite effect.

Abstract: Circuits employing an adjacent low-k dummy gate to a field-effect transistor (FET) to reduce FET source/drain parasitic capacitance, and related fabrication methods. To reduce or mitigate an increase in the source/drain parasitic capacitance(s) of a FET, a dummy gate adjacent to an active gate of the FET is provided to have a low-k (i.e., low relative permittivity). In this manner, the relative permittivity (k) between the source/drain of the FET and an adjacent dummy gate and/or source/drain of another FET is reduced, thereby reducing the parallel plate capacitance of the FET(s). Reducing parasitic capacitance of the FET(s) may allow further reduced scaling of the circuit to offset or mitigate a lack of reduction or increase in parasitic capacitance as a result of reducing gate pitch in the circuit. As gate pitch is reduced in the circuit, it may not be possible to proportionally reduce gate size without sacrificing gate control.

Abstract: Aspects disclosed herein include circuits employing a double diffusion break (DDB) and a single diffusion break (SDB) in different type diffusion regions, and related fabrication methods are disclosed. In exemplary aspects disclosed herein, either a DDB or a SDB is formed in the N-type diffusion region(s) and the opposing type diffusion, either a SDB or DDB, is formed in the P-type diffusion region(s). Forming different diffusion breaks between a DDB and a SDB in different diffusion regions of the circuit can be employed to induce channel strain that will increase carrier mobility of either P-type or N-type semiconductor devices formed in respective P-type or N-type diffusion region(s), while avoiding or reducing such induced channel strain in either P-type or N-type semiconductor devices formed in respective P- or N-type diffusion region(s) that may degrade carrier mobility.

Abstract: Middle-of-line (MOL) complementary power rail(s) in integrated circuits (ICs) for reduced semiconductor device resistance, and related methods are disclosed. In exemplary aspects, to reduce or mitigate an increase in resistance in the cell power rails in the IC, a complementary power rail(s) is formed in a MOL layer(s) of the IC and coupled to cell power rail(s) formed in a metal layer in a front-end-of-line (FEOL) layer in the IC. In exemplary aspects, the MOL layer(s) in which the complementary power rail is formed is in a layer below the metal layer in the FEOL layer in which the cell power rail is formed. The complementary power rail has the effect of reducing the resistance of the cell power rail, and thus has the effect of reducing the resistance of FET(s) coupled to the cell power rail thereby increasing performance.

Abstract: Aspects disclosed herein include circuits employing a double diffusion break (DDB) and a single diffusion break (SDB) in different type diffusion regions, and related fabrication methods are disclosed. In exemplary aspects disclosed herein, either a DDB or a SDB is formed in the N-type diffusion region(s) and the opposing type diffusion, either a SDB or DDB, is formed in the P-type diffusion region(s). Forming different diffusion breaks between a DDB and a SDB in different diffusion regions of the circuit can be employed to induce channel strain that will increase carrier mobility of either P-type or N-type semiconductor devices formed in respective P-type or N-type diffusion region(s), while avoiding or reducing such induced channel strain in either P-type or N-type semiconductor devices formed in respective P- or N-type diffusion region(s) that may degrade carrier mobility.

Abstract: A wavelength division multiplexed (WDM) reconfigurable optical switch, the switch has at least one optical input port to receive a WDM input optical signal comprising a plurality of wavelength channels; a plurality of optical output ports; a reconfigurable holographic array on an optical path between the at least one optical input port and the plurality of optical output ports; and at least one diffractive element on an optical path between at least one optical input port and the reconfigurable holographic array, to demultiplex the WDM input optical signal into a plurality of demultiplexed optical input beam channels, and to disperse the demultiplexed optical input beam channels spatially along a first axis on said the reconfigurable holographic array; and the switch further comprises one or more beam profiling optical elements to modify transverse beam profiles of the demultiplexed optical input beam channels.

Abstract: We describe a space-division multiplexed (SDM) fibre, reconfigurable, wavelength-selective switch (WSS).

Abstract: Aspects disclosed herein include circuits employing a double diffusion break (DDB) and a single diffusion break (SDB) in different type diffusion regions, and related fabrication methods are disclosed. In exemplary aspects disclosed herein, either a DDB or a SDB is formed in the N-type diffusion region(s) and the opposing type diffusion, either a SDB or DDB, is formed in the P-type diffusion region(s). Forming different diffusion breaks between a DDB and a SDB in different diffusion regions of the circuit can be employed to induce channel strain that will increase carrier mobility of either P-type or N-type semiconductor devices formed in respective P-type or N-type diffusion region(s), while avoiding or reducing such induced channel strain in either P-type or N-type semiconductor devices formed in respective P- or N-type diffusion region(s) that may degrade carrier mobility.

Abstract: A cell circuit includes a first power rail, having a first line length, in a first layer. The first power rail is configured to receive a first voltage for the cell circuit. The cell circuit includes multiple lines in a second layer and a shunt in a third layer. The shunt is electrically coupled to the first power rail and a first set of lines of the multiple lines. The shunt has a second line length shorter than the first line length. The cell circuit includes another shunt in t the third layer. The other shunt is also parallel to the first power rail. The other shunt is electrically coupled to the first power rail and a second set of lines of the multiple lines. The other shunt has a third line length shorter than the first line length.