Abstract: A fin field effect transistors (FinFET) array includes a first transistor having a fin and a first conductive gate on the fin. The FinFET array also includes a second transistor having another fin and a second conductive gate on the other fin. The FinFET array further includes a first dielectric material and a self-aligned dielectric spacer. The first dielectric material is between the first transistor and the second transistor and on at least a portion of sidewalls of each of the first conductive gate and the second conductive gate. The self-aligned dielectric spacer is on at least a portion of the sidewalls of each of the first conductive gate and the second conductive gate.

Abstract: We describe a wavelength division multiplexed (WDM) reconfigurable optical switch, the switch comprising: a set of arrays of optical beam connections, each comprising an array of optical outputs and having an optical input to receive a WDM input optical signal; a first diffractive element to demultiplexed said WDM input optical signal into a plurality of demultiplexed optical input beams, and to disperse said demultiplexed optical input beams spatially along a first axis; first relay optics between said set of arrays of optical beam connections and said first diffractive element; and a reconfigurable holographic array comprising a 2D array of reconfigurable sub-holograms defining sub-hologram rows and columns; wherein said arrays of said set of arrays are at least one dimensional arrays extending spatially in a direction parallel to said first axis and arranged in a column defining a second axis orthogonal to said first axis; wherein said sub-hologram rows are aligned along said first axis, and wherein said s

Abstract: A semiconductor device includes a substrate, a gate region formed on the substrate, a self-aligned gate cut formed in the gate region, and a middle of line (MOL) area formed on the gate region, wherein the self-aligned gate cut provides critical dimensions in a range from 5 nm to 30 nm. The self-aligned gate cut reduces capacitance and power, provides flexibility in placement of the MOL area, and reduces local routing congestion.

Abstract: Methods, systems, and devices for an artificial neural network are described. In one example, an artificial neuron in an artificial neural network may include a resistor coupled with an input line and configured to indicate a synaptic weight and a fuse coupled with the resistor. The artificial neuron may also include a selection component coupled with the fuse and configured to activate the fuse for programming the resistor, and a second selection component coupled with the resistor and an output line, the second selection component configured to select the resistor for a read operation.

Abstract: A wavelength division multiplexed (WDM) reconfigurable optical switch. The switch has a set of arrays of optical beam connections, each comprising an array of optical outputs and having an optical input to receive a WDM input optical signal; a first diffractive element to demultiplexed the WDM input optical signal into a plurality of demultiplexed optical input beams, and to disperse said demultiplexed optical input beams spatially along a first axis; first relay optics between the set of arrays of optical beam connections and the first diffractive element; and a reconfigurable holographic array comprising a 2D array of reconfigurable sub-holograms defining sub-hologram rows and columns. The arrays of said set of arrays and the sub-hologram rows and columns are arranged and aligned in particular ways so that wavelength channels of the WDM input signal for each array can be steered within the device towards a selected optical output.

Abstract: Integrated circuits (ICs) employing additional output vertical interconnect access(es) (via(s)) coupled to a circuit output via to decrease circuit output resistance and related methods are disclosed. In exemplary aspects, an output metal interconnect is formed in the IC that extends between a first output contact connected to an output transistor(s) of a circuit, and across an adjacent dummy gate to a second output contact area on the opposite side of the dummy gate from the signal output node. A second output via is connected to the output metal interconnect in the second output contact area. A metal line in a metal layer above the diffusion area and metal contacts is connected to the output via and second output via having parallel output via resistances to reduce the output via resistance of the output transistor(s) of the circuit, and thus reduces the overall resistance of the signal output node of the circuit.

Abstract: An integrated circuit (IC) employs a channel structure layout having an active semiconductor channel structure(s) and an isolated neighboring dummy semiconductor channel structure(s) for increased uniformity. A semiconductor channel structure(s) in an IC is a fin structure(s) or a gate-all-around (GAA) structure(s) employed in a Field-Effect Transistor (FET), such as a FinFET or a three-dimensional (3D) FET. The channel structures in the IC are fabricated according to a circuit cell architecture, such as a standard circuit cell (“standard cell”). The IC includes an active (e.g., diffusion) region in which a semiconductor channel structure array (e.g., semiconductor fin array) is formed according to a pattern. The IC includes a device employing a channel structure array in the active region. The channel structure array may include one active channel structure (e.g., fin) for reduced power consumption in the FinFET, and may include at least one dummy fin for increased uniformity.

Abstract: Asymmetric gated fin field effect transistor (FET) (finFET) diodes are disclosed. In one aspect, an asymmetric gated finFET diode employs a substrate that includes a well region of a first-type and a fin disposed in a direction. A first source/drain region is employed that includes a first-type doped material disposed in the fin having a first length in the direction. A second source/drain region having a second length in the direction larger than the first length is employed that includes a second-type doped material disposed in the fin. A gate region is disposed between the first source/drain region and the second source/drain region and has a third length in the direction that is larger than the first length and larger than the second length. The wider gate region increases a length of a depletion region of the asymmetric gated finFET diode, which reduces current leakage while avoiding increase in area.

Abstract: Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance are disclosed. To speed up performance of selected circuits in an IC that would otherwise lower overall speed performance of the IC, low-K dielectric material is employed during IC fabrication. The low-K dielectric material is provided in selected, localized areas of ILD material in which selected circuits are disposed. In this manner, the IC will experience an overall increased speed performance during operation, because circuit components and/or circuit element interconnects of selected circuit(s) that are disposed in the low-K ILD material will experience reduced signal delay.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.

Abstract: Semiconductor devices employing Field Effect Transistors (FETs) with multiple channel structures without shallow trench isolation (STI) void-induced electrical shorts are disclosed. In one aspect, a semiconductor device is provided that includes a substrate. The semiconductor device includes channel structures disposed over the substrate, the channel structures corresponding to a FET. An STI trench is formed between each corresponding pair of channel structures. Each STI trench includes a bottom region filled with a lower quality oxide, and a top region filled with a higher quality oxide. The lower quality oxide is susceptible to void formation in the bottom region during particular fabrication steps of the semiconductor device. However, the higher quality oxide is not susceptible to void formation. Thus, the higher quality oxide does not include voids with which a gate may electrically couple to other active components, thus preventing STI void-induced electrical shorts in the semiconductor device.

Abstract: To avoid the problems associated with low density spin on dielectrics, some examples of the disclosure include a finFET with an oxide material having different densities. For example, one such finFET may include an oxide material located in a gap between adjacent fins, the oxide material directly contacts the adjacent fins of the plurality of fins with a first density proximate to a top layer of the oxide material and a second density proximate to a bottom layer of the oxide material and wherein the first density is greater than the second density.

Abstract: A wavelength division multiplexed (WDM) reconfigurable optical switch, the switch has at least one optical input port to receive a WDM input optical signal comprising a plurality of wavelength channels; a plurality of optical output ports; a reconfigurable holographic array on an optical path between the at least one optical input port and the plurality of optical output ports; and at least one diffractive element on an optical path between at least one optical input port and the reconfigurable holographic array, to demultiplex the WDM input optical signal into a plurality of demultiplexed optical input beam channels, and to disperse the demultiplexed optical input beam channels spatially along a first axis on said the reconfigurable holographic array; and the switch further comprises one or more beam profiling optical elements to modify transverse beam profiles of the demultiplexed optical input beam channels.

Abstract: A wavelength division multiplexed (WDM) reconfigurable optical switch. The switch has a set of arrays of optical beam connections, each comprising an array of optical outputs and having an optical input to receive a WDM input optical signal; a first diffractive element to demultiplexed the WDM input optical signal into a plurality of demultiplexed optical input beams, and to disperse said demultiplexed optical input beams spatially along a first axis; first relay optics between the set of arrays of optical beam connections and the first diffractive element; and a reconfigurable holographic array comprising a 2D array of reconfigurable sub-holograms defining sub-hologram rows and columns.

Abstract: A sacrificial cap is grown on an upper surface of a conductor. A dielectric spacer is against a side of the conductor. An upper dielectric side spacer is formed on a sidewall of the sacrificial cap. The sacrificial cap is selectively etched, leaving a cap recess, and the upper dielectric side spacer facing the cap recess. Silicon nitride is filled in the cap recess, to form a center cap and a protective cap having center cap and the upper dielectric spacer.

Abstract: To avoid the problems associated with low density spin on dielectrics, some examples of the disclosure include a finFET with an oxide material having different densities. For example, one such finFET may include an oxide material located in a gap between adjacent fins, the oxide material directly contacts the adjacent fins of the plurality of fins with a first density proximate to a top layer of the oxide material and a second density proximate to a bottom layer of the oxide material and wherein the first density is greater than the second density.

Abstract: A device includes a source contact, a drain contact, a gate contact, and a body contact. The body contact is electrically coupled to a temperature sensing circuit. The source contact, the drain contact, the gate contact, and the body contact are included in a fin field-effect transistor (finFET).

Abstract: Asymmetric gated fin field effect transistor (FET) (finFET) diodes are disclosed. In one aspect, an asymmetric gated finFET diode employs a substrate that includes a well region of a first-type and a fin disposed in a direction. A first source/drain region is employed that includes a first-type doped material disposed in the fin having a first length in the direction. A second source/drain region having a second length in the direction larger than the first length is employed that includes a second-type doped material disposed in the fin. A gate region is disposed between the first source/drain region and the second source/drain region and has a third length in the direction that is larger than the first length and larger than the second length. The wider gate region increases a length of a depletion region of the asymmetric gated finFET diode, which reduces current leakage while avoiding increase in area.

Abstract: The n-type to p-type fin-FET strength ratio in an integrated logic circuit may be tuned by the use of cut regions in the active and dummy gate electrodes. In some examples, separate cut regions for the dummy gate electrodes and the active gate electrode may be used to allow for different lengths of gate pass-active regions resulting in appropriately tuned integrated logic circuits.

Abstract: Semiconductor devices with wider field gates for reduced gate resistance are disclosed. In one aspect, a semiconductor device is provided that employs a gate. The gate is a conductive line disposed above the semiconductor device to form transistors corresponding to active semiconductor regions. Each active semiconductor region has a corresponding channel region. Portions of the gate disposed over each channel region are active gates, and portions not disposed over the channel region, but that are disposed over field oxide regions, are field gates. A voltage differential between each active gate and a source of each corresponding transistor causes current flow in a channel region when the voltage differential exceeds a threshold voltage. The width of each field gate is a larger width than each active gate. The larger width of the field gates results in reduced gate resistance compared to devices with narrower field gates.