Patents by Inventor Haitao Cheng

Haitao Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200393014
    Abstract: A pre-compression type emergency air spring assembly includes an upper cover plate, an air bag, an upper end plate, and a lower end plate. A periphery of the upper end plate is connected with a periphery of the lower end plate through the air bag. A top part of the upper end plate is provided with transverse pre-compression cavities and transverse pre-compression plates arranged at transverse openings of the transverse pre-compression cavities. The transverse pre-compression cavities are internally provided with laminated spring elastomers through the transverse pre-compression plates in a pressing mode. Multiple steel springs are arranged between the upper cover plate and the upper end plate in a pressing mode along a circumferential direction of the laminated spring elastomers. The upper cover plate is arranged on a periphery of the transverse pre-compression cavities in a sleeving mode.
    Type: Application
    Filed: August 2, 2018
    Publication date: December 17, 2020
    Applicant: ZHUZHOU TIMES NEW MATERIAL TECHNOLOGY CO.,LTD.
    Inventors: Duomin NONG, Te YE, Canhui CHEN, Haitao CHENG, Jun ZHOU, Qiang CHEN, Guoqi DUAN, Qinghua CHEN, Yaokun LONG
  • Patent number: 10861793
    Abstract: Aspects generally relate to tuning a guard ring in an integrated circuit. A guard ring with a gap surrounds a circuit. The level of isolation provided by the guard ring at a particular frequency can be adjusted by coupling a tuning circuit cross the gap of the guard ring. If the circuit in the guard ring is an inductive circuit the level of inductance at a particular frequency can be adjusted by selecting the appropriate tuning circuit across the gap of the guard ring.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: December 8, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Haitao Cheng, Ye Lu, Chao Song
  • Patent number: 10840872
    Abstract: A low-pass filter having a notch frequency due to a resonance between a mutual inductance of inductive elements and a capacitance. An exemplary low-pass filter generally includes a first inductive element having a first terminal and a second terminal, the first terminal being coupled to the input port, and a second inductive element having a first terminal and a second terminal, the first terminal of the second inductive element being coupled to the second terminal of the first inductive element and the second terminal of the second inductive element being coupled to the output port. The filter also includes a shunt capacitive element coupled to the second terminal of the first inductive element, wherein a mutual inductance between the first inductive element and the second inductive element and a capacitance of the shunt capacitive element are configured to have a resonance providing a notch frequency for the low-pass filter.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: November 17, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Haitao Cheng, Yanming Xiao, Wu-Hsin Chen, Li Liu, Masoud Moslehi Bajestan
  • Publication number: 20200266791
    Abstract: A low-pass filter having a notch frequency due to a resonance between a mutual inductance of inductive elements and a capacitance. An exemplary low-pass filter generally includes a first inductive element having a first terminal and a second terminal, the first terminal being coupled to the input port, and a second inductive element having a first terminal and a second terminal, the first terminal of the second inductive element being coupled to the second terminal of the first inductive element and the second terminal of the second inductive element being coupled to the output port. The filter also includes a shunt capacitive element coupled to the second terminal of the first inductive element, wherein a mutual inductance between the first inductive element and the second inductive element and a capacitance of the shunt capacitive element are configured to have a resonance providing a notch frequency for the low-pass filter.
    Type: Application
    Filed: February 14, 2019
    Publication date: August 20, 2020
    Inventors: Haitao CHENG, Yanming XIAO, Wu-Hsin CHEN, Li LIU, Masoud MOSLEHI BAJESTAN
  • Publication number: 20200217388
    Abstract: A prepressed emergency air spring assembly includes an upper cover plate, an air bag, an upper end plate and a lower end plate. The periphery of the upper end plate is connected with an outer periphery of the lower end plate through the air bag. A steel spring is arranged between the upper cover plate and the upper end plate in a pressing mode. A plurality of hourglass elastomers are arranged between the upper cover plate and the upper end plate along a circumferential direction of the steel spring.
    Type: Application
    Filed: August 2, 2018
    Publication date: July 9, 2020
    Applicant: ZHUZHOU TIMES NEW MATERIAL TECHNOLOGY CO.,LTD.
    Inventors: Duomin NONG, Te YE, Canhui CHEN, Haitao CHENG, Jun ZHOU, Qiang CHEN, Guoqi DUAN, Qinghua CHEN, Yaokun LONG
  • Publication number: 20200217390
    Abstract: A combined air spring system includes an upper cover plate, an air bag, an upper end plate and a lower end plate. An outer periphery of the upper cover plate is connected with an outer periphery of the upper end plate through the air bag. A low-position sand clock elastomer is connected between the upper end plate and the lower end plate . A pressing plate is installed at a bottom portion of the upper cover plate, and a high-position elastomer is connected between the upper cover plate and the pressing plate. A limiting table is arranged at a bottom portion of the pressing plate. A limiting groove is formed in a top face of the upper end plate. The limiting table is located in the limiting groove in a deflated state.
    Type: Application
    Filed: August 2, 2018
    Publication date: July 9, 2020
    Applicant: ZHUZHOU TIMES NEW MATERIAL TECHNOLOGY CO.,LTD.
    Inventors: Te YE, Duomin NONG, Canhui CHEN, Haitao CHENG, Jun ZHOU, Qiang CHEN, Wenhai CHEN, Zhuangbing JIN, Xuan PENG
  • Publication number: 20200217387
    Abstract: An emergency air spring assembly includes an upper cover plate, an air bag, an upper end plate and a lower end plate. An outer periphery of the upper end plate is connected with an outer periphery of the lower end plate through the air bag. An hourglass elastomer is connected between the upper cover plate and the upper end plate. A plurality of steel springs are arranged between the upper cover plate and the upper end plate in a circumferential direction of the sand clock elastomer in a pressing mode.
    Type: Application
    Filed: August 2, 2018
    Publication date: July 9, 2020
    Applicant: ZHUZHOU TIMES NEW MATERIAL TECHNOLOGY CO.,LTD.
    Inventors: Duomin NONG, Te YE, Canhui CHEN, Haitao CHENG, Jun ZHOU, Qiang CHEN, Guoqi DUAN, Qinghua CHEN, Yaokun LONG
  • Publication number: 20200208703
    Abstract: An hourglass type air spring assembly includes an upper cover plate, an air bag, an upper end plate and a lower end plate. An outer periphery of the upper cover plate is connected with an outer periphery of the upper end plate through the air bag. A low-position hourglass elastomer and a high-position elastomer which are integrally formed are connected with each other between the upper end plate and the lower end plate. An annular notch is formed between the low-position hourglass elastomer and the high-position elastomer, and an annular rigid partition plate matched with the annular notch is arranged in the annular notch.
    Type: Application
    Filed: August 2, 2018
    Publication date: July 2, 2020
    Applicant: ZHUZHOU TIMES NEW MATERIAL TECHNOLOGY CO., LTD.
    Inventors: Wenhai CHEN, Te YE, Canhui CHEN, Haitao CHENG, Xuan PENG, Zhuangbing JIN, Jun ZHOU, Qiang CHEN
  • Patent number: 10665370
    Abstract: A co-wound resistor with a low parasitic inductance includes a first resistive strip having an input and a second resistive strip having an output. The second resistive strip has a similar shape as the first resistive strip. The second resistive strip is co-wound in a same direction as the first resistive strip. The second resistive strip and the first resistive strip are configured to generate a mutual inductance that cancels an inductance of the first resistive strip and the second resistive strip. The first interconnect coupling the first resistive strip to the second resistive strip. The first resistive strip, the second resistive strip and the first interconnect are on a same level.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: May 26, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Haitao Cheng, Chao Song, Ye Lu
  • Patent number: 10651268
    Abstract: A capacitor has reduced misalignment in the interconnect layers and lower capacitance variance. The capacitor includes a first endcap having a first section and a second section orthogonal to the first section. The capacitor includes a first set of conductive fingers orthogonally coupled to the first section. The capacitor includes a third set of conductive fingers orthogonally coupled to the second section of the endcap and a second endcap parallel to the first section of the endcap. The capacitor includes a second set of conductive fingers orthogonally coupled to a second endcap and interdigitated with the first set of conductive fingers at a first interconnect layer. The capacitor includes a third endcap parallel to the second section of the first endcap and a fourth set of conductive fingers orthogonally coupled to the third endcap and interdigitated with the third set of conductive fingers at the first interconnect layer.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: May 12, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Haitao Cheng, Ye Lu, Chao Song
  • Patent number: 10643985
    Abstract: An integrated circuit (IC) includes a capacitor array in at least one first back-end-of-line (BEOL) interconnect level. The capacitor array includes a pair of capacitor manifolds coupled to parallel capacitor routing traces and capacitors coupled between each pair of parallel capacitor routing traces. The IC also includes an inductor trace having at least one turn in at least one second BEOL interconnect level. The inductor trace defines a perimeter to overlap at least a portion of the capacitor array.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: May 5, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Haitao Cheng, Zhang Jin
  • Patent number: 10629523
    Abstract: Certain aspects of the present disclosure provide an integrated circuit (IC) that includes at least one of a via-based vertical capacitor structure or a via-based vertical resistor structure. The IC includes a substrate oriented in a horizontal plane, electrically conductive layers disposed above the substrate, and electrically insulative layers disposed above the substrate and interposed between the plurality of electrically conductive layers. At least one of the vertical capacitor structure or the vertical resistor structure is disposed in the electrically conductive layers and the electrically insulative layers.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: April 21, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Chao Song, Ye Lu, Haitao Cheng
  • Patent number: 10629590
    Abstract: A resistor-capacitor (RC) delay circuit includes a first capacitor at a first level, a resistor at a second level and a second capacitor at a third level. The second capacitor is electrically connected in parallel with the first capacitor. The second capacitor has a footprint within a footprint of the first capacitor. The resistor is coupled in shunt with the first capacitor and the second capacitor.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: April 21, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Ye Lu, Chao Song, Haitao Cheng
  • Publication number: 20200118921
    Abstract: Certain aspects of the present disclosure provide a metal-on-metal (MoM) capacitor with metal layers, each layer having two different electrical conductors with orthogonally-arranged conductive arteries and orthogonally-oriented conductive fingers. One exemplary MoM capacitor generally includes a plurality of metal layers, wherein a first metal layer in the plurality of metal layers comprises a first electrical conductor providing a first node of the MoM capacitor and a second electrical conductor providing a second node of the MoM capacitor. According to aspects, the first electrical conductor comprises a first plurality of conductive fingers and the second electrical conductor comprises a second plurality of conductive fingers. Further, conductive fingers of the first plurality of conductive fingers are interdigitated with conductive fingers of the second plurality of conductive fingers.
    Type: Application
    Filed: October 12, 2018
    Publication date: April 16, 2020
    Inventors: Haitao CHENG, Ye LU, Chao SONG
  • Publication number: 20200111145
    Abstract: Embodiments of the present invention disclose a product material integration and orchestration method and a cloud service apparatus, to provide an automated orchestration service, improve orchestration quality and efficiency, and satisfy a requirement for on-demand customization of product material. The method in the embodiments of the present invention includes: obtaining target content, where the target content includes at least one of the following content: user-generated semantic content, existing semantic content, and semantic content in an orchestration system; and orchestrating the target content based on a product model and an information model, to obtain a product information deliverable.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Inventors: Hong YI, Haitao CHENG
  • Publication number: 20200111865
    Abstract: A low cost capacitor (e.g., metal-insulator-metal (MIM) capacitor) is included in the back-end-of-line layers for effective routing and area savings. The capacitor has a first electrode (e.g., a first terminal of the capacitor) including a conductive back-end-of-line (BEOL) layer and a second electrode (e.g., a second terminal of the capacitor) including a nitride-based metal. The capacitor also has an etch stop layer (e.g., a dielectric of the capacitor) between the first electrode and the second electrode.
    Type: Application
    Filed: October 9, 2018
    Publication date: April 9, 2020
    Inventors: Ye LU, Junjing BAO, Haitao CHENG, Chao SONG
  • Patent number: 10600731
    Abstract: An integrated circuit includes a capacitor (e.g., a folded metal-oxide-metal (MOM) capacitor) formed in the lower BEOL interconnect levels, without degrading an inductor's Q-factor. The integrated circuit includes the capacitor in one or more back-end-of-line (BEOL) interconnect levels. The capacitor includes multiple folded capacitor fingers having multiple sides and a pair of manifolds on a same side of the folded capacitor fingers. Each of the pair of manifolds is coupled to one or more of the folded capacitor fingers. The integrated circuit also includes an inductive trace having one or more turns in one or more different BEOL interconnect levels. The inductive trace overlaps one or more portions of the capacitor.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: March 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Haitao Cheng, Zhang Jin
  • Patent number: 10600569
    Abstract: Methods, systems, and devices for a finger metal-on-metal (FMOM) capacitor including a negative capacitance material are described. In one examples, a FMOM capacitor may include a first electrode and a second electrode. The FMOM capacitor may include a dielectric layer coating a first sidewall of the first electrode and a second sidewall of a second electrode. A portion of the first sidewall may be substantially parallel to a portion of the second sidewall. The FMOM capacitor may also include a negative capacitance material disposed in a channel between the first sidewall of the first electrode and the second sidewall of the second electrode. The negative capacitance material may extend in a direction that is substantially parallel to the portion of the first sidewall and the portion of the second sidewall.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: March 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Ye Lu, Haitao Cheng, Chao Song
  • Publication number: 20200083158
    Abstract: Certain aspects of the present disclosure provide an integrated circuit (IC) that includes at least one of a via-based vertical capacitor structure or a via-based vertical resistor structure. The IC includes a substrate oriented in a horizontal plane, electrically conductive layers disposed above the substrate, and electrically insulative layers disposed above the substrate and interposed between the plurality of electrically conductive layers. At least one of the vertical capacitor structure or the vertical resistor structure is disposed in the electrically conductive layers and the electrically insulative layers.
    Type: Application
    Filed: September 10, 2018
    Publication date: March 12, 2020
    Inventors: Chao SONG, Ye LU, Haitao CHENG
  • Publication number: 20200075582
    Abstract: A resistor-capacitor (RC) delay circuit includes a first capacitor at a first level, a resistor at a second level and a second capacitor at a third level. The second capacitor is electrically connected in parallel with the first capacitor. The second capacitor has a footprint within a footprint of the first capacitor. The resistor is coupled in shunt with the first capacitor and the second capacitor.
    Type: Application
    Filed: August 28, 2018
    Publication date: March 5, 2020
    Inventors: Ye LU, Chao SONG, Haitao CHENG