Patents by Inventor Hajime Akiyama
Hajime Akiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140202364Abstract: A waste-melting method, in which waste is fed into a waste-melting furnace (1), and the waste is thermally decomposed and combusted, and then, thermal decomposition and combustion residues are melted, is characterized in that coal coke and a biomass-molded material obtained by press-molding a biomass starting material while heating the biomass starting material to a temperature lower than the carbonization temperature thereof are fed into the melting furnace, a high-temperature grate is formed with coal coke at the bottom of the melting furnace, and the coal coke and the biomass-molded material are combusted and used as heat sources for melting.Type: ApplicationFiled: May 23, 2012Publication date: July 24, 2014Applicants: KINKI UNIVERSITY, JFE ENGINEERING CORPORATIONInventors: Takashi Nakayama, Takeshi Uchiyama, Hajime Akiyama, Tomohiro Yoshida, Tamio Ida
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Publication number: 20140077284Abstract: In one surface of a semiconductor substrate, an active region in which main current flows and an IGBT is disposed is formed. A termination structure portion serving as an electric-field reduction region is formed laterally with respect to the active region. In the termination structure portion, a porous-oxide-film region, a p-type guard ring region, and an n+-type channel stopper region are formed. A plurality of floating electrodes are formed to contact the surface of the porous-oxide-film region. Another plurality of floating electrodes are formed to contact a first insulating film.Type: ApplicationFiled: May 31, 2013Publication date: March 20, 2014Inventors: Hajime AKIYAMA, Akira OKADA
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Publication number: 20140015554Abstract: An inspection apparatus includes an insulating substrate, a socket in which a body portion having a through-hole in a wall thereof is integrally formed with a connection portion secured to the insulating substrate, and a contact probe detachably secured to the socket.Type: ApplicationFiled: March 4, 2013Publication date: January 16, 2014Applicant: Mitsubishi Electric CorporationInventors: Akira OKADA, Hajime AKIYAMA, Kinya YAMASHITA
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Publication number: 20140009183Abstract: A semiconductor testing jig fixes a measurement target while it is held between a chuck stage and the measurement target. The semiconductor testing jig includes a base on which the measurement target is to be installed and which can be attached to the chuck stage. The base includes: a first main surface to become an installation surface for the measurement target; a second main surface opposite the first main surface and which is to contact the chuck stage; and a porous region containing a porous member. The porous region is provided selectively as seen in plan view, and penetrates through the base from the first main surface toward the second main surface.Type: ApplicationFiled: March 14, 2013Publication date: January 9, 2014Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Hajime AKIYAMA, Akira OKADA, Kinya YAMASHITA
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Patent number: 8609443Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.Type: GrantFiled: November 1, 2012Date of Patent: December 17, 2013Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuhiro Shimizu, Hajime Akiyama, Naoki Yasuda
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Publication number: 20130321019Abstract: It is an object of the present invention to provide a probe card capable of controlling generation of a scratch or an indentation in a connection pad and capable of controlling generation of heat in a connection pad and its vicinity having contacted a contact probe at low cost and in a simple way. A probe card includes a probe substrate, at least one contact probe electrically connected to a signal line provided to an insulating base of the probe substrate and fixed to the insulating base, and at least one engagement member installed on the contact probe at a position near a tip end portion of the contact probe. The engagement member has at least one engagement portion that makes abutting contact with another predetermined member during operation to restrain the operation of the contact probe.Type: ApplicationFiled: March 1, 2013Publication date: December 5, 2013Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Akira OKADA, Hajime AKIYAMA, Kinya YAMASHITA
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Publication number: 20130321015Abstract: An inspection apparatus includes an insulating substrate, a probe pin having a body portion secured to the insulating substrate, a tip portion connected to one end of the body portion and disposed on the back surface side of the insulating substrate, and a connection portion connected to the other end of the body portion and disposed on the front surface side of the insulating substrate, and a heat-radiating terminal in contact with the connection portion, wherein a current is applied through the heat-radiating terminal and the probe pin to an object to measured, and wherein the heat-radiating terminal discharges heat from the probe pin.Type: ApplicationFiled: March 1, 2013Publication date: December 5, 2013Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Akira OKADA, Hajime AKIYAMA, Kinya YAMASHITA
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Publication number: 20130285684Abstract: An inspection apparatus includes a probe substrate, a socket secured to the probe substrate, a heating element wire wound around the socket, a probe tip detachably connected to the socket, a stage on which an object to be measured is mounted, and a heating unit for heating the stage.Type: ApplicationFiled: January 14, 2013Publication date: October 31, 2013Inventors: Akira OKADA, Hajime AKIYAMA, Kinya YAMASHITA
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Publication number: 20130256964Abstract: A method of attaching a wafer by suction, includes a step of mounting a wafer on a right arm and a left arm of a transfer jig, moving the transfer jig toward a wafer suction stage in such a manner that a facing right arm surface of the right arm slides along and in contact with a first side surface of the wafer suction stage and a facing left arm surface of the left arm slides along and in contact with a second side surface of the wafer suction stage until the wafer comes to lie directly above a mounting surface of the wafer suction stage, mounting the wafer on the mounting surface by moving the transfer jig downward toward the wafer suction stage while maintaining the contacts, and attaching the wafer to the mounting surface by suction.Type: ApplicationFiled: September 14, 2012Publication date: October 3, 2013Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Hajime AKIYAMA, Akira OKADA, Kinya YAMASHITA
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Publication number: 20130192630Abstract: A device includes a jig having a plate with through-holes formed therein and also having a frame formed on the plate so as to be able to accommodate a plurality of semiconductor chips in spaced relationship, a foreign matter capture member having a first charge section with a first flat surface and a second charge section with a second flat surface, the second charge section being insulated from the first charge section, charging means for positively charging the first flat surface and negatively charging the second flat surface, and sliding means for causing either the jig or the foreign matter capture member to slide relative to the other in such a manner that the through-holes of the jig face and are spaced a predetermined distance from the first and second flat surfaces. The through-holes are formed in different regions defined and surrounded by the frame.Type: ApplicationFiled: September 14, 2012Publication date: August 1, 2013Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Akira OKADA, Takaya NOGUCHI, Hajime AKIYAMA
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Publication number: 20130152965Abstract: A semiconductor cleaning device includes an external electrode opposed to a side surface of the semiconductor device; a base configured to allow arrangement of the semiconductor device, and having an opening positioned between the side surface of the semiconductor device in the arranged state and the external electrode, and located below the side surface of the semiconductor device; a frame having an electrically insulating property, being in contact with the external electrode, arranged on the base and opposed to the side surface of the semiconductor device; and suction means connected to the opening in the base and being capable of taking in the foreign matter through the opening. Thereby, the semiconductor cleaning device and a semiconductor cleaning method that can remove the foreign matter adhered to the side surface of the semiconductor device and can prevent re-adhesion of the removed foreign matter can be obtained.Type: ApplicationFiled: August 27, 2012Publication date: June 20, 2013Applicant: Mitsubishi Electric CorporationInventors: Akira OKADA, Takaya Noguchi, Hajime Akiyama
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Publication number: 20130056791Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.Type: ApplicationFiled: November 1, 2012Publication date: March 7, 2013Inventors: Kazuhiro SHIMIZU, Hajime Akiyama, Naoki Yasuda
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Patent number: 8324657Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.Type: GrantFiled: June 14, 2011Date of Patent: December 4, 2012Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuhiro Shimizu, Hajime Akiyama, Naoki Yasuda
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Publication number: 20120161751Abstract: A semiconductor device comprises: a semiconductor element including an electrode; a leading line electrically connected to the electrode, passing above the electrode, and led to a side thereof; and a current sensor sensing current flowing through the leading line. The current sensor includes a magneto-resistance element placed above the electrode and below the leading line. A resistance value of the magneto-resistance element varies linearly according to magnetic field generated by the current.Type: ApplicationFiled: August 19, 2011Publication date: June 28, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Hajime Akiyama, Akira Okada
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Patent number: 8125045Abstract: A dielectric isolation type semiconductor device includes a dielectric isolation type substrate in which a support substrate, an embedded dielectric layer, and a first conductive type semiconductor substrate of a low impurity concentration are laminated one over another. The semiconductor substrate includes a first semiconductor region of a first conductive type having a high impurity concentration, a second semiconductor region of a second conductive type having a high impurity concentration arranged so as to surround the first semiconductor region, a first main electrode joined to a surface of the first semiconductor region, and a second main electrode joined to a surface of the second semiconductor region. A first dielectric portion is arranged adjacent the embedded dielectric layer so as to surround a region of the support substrate superposed on the first semiconductor region in a direction of lamination thereof, and a wire connected with the first main electrode.Type: GrantFiled: December 29, 2008Date of Patent: February 28, 2012Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Hajime Akiyama
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Patent number: 8110449Abstract: The HVIC includes a dielectric layer and an SOI active layer stacked on a silicon substrate, a transistor formed in the surface of the SOI active layer, and a trench isolation region formed around the transistor. The dielectric layer includes a first buried oxide film formed in the surface of the silicon substrate, a shield layer formed below the first buried oxide film opposite the element area, a second buried oxide film formed around the shield layer, and a third buried oxide film formed below the shield layer and the second buried oxide film. Therefore, the potential distribution curves PC within the dielectric layer are low in density and a high withstand voltage is achieved.Type: GrantFiled: November 8, 2010Date of Patent: February 7, 2012Assignee: Mitsubishi Electric CorporationInventor: Hajime Akiyama
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Patent number: 8071454Abstract: A method for manufacturing a dielectric isolation type semiconductor device comprises: forming a plurality of trenches in a first region on a major surface of a semiconductor substrate; forming a first dielectric layer on the major surface of the semiconductor substrate and a first thick dielectric layer in the first region by oxidizing a surface of the semiconductor substrate; bonding a semiconductor layer of a first conductive type to the semiconductor substrate via the first dielectric layer; forming a first semiconductor region by implanting an impurity into a part of the semiconductor layer above the first thick dielectric layer; forming a second semiconductor region by implanting an impurity of a second conductive type into a part of the semiconductor layer so as to surround the first semiconductor region separating from the first semiconductor region.Type: GrantFiled: December 3, 2010Date of Patent: December 6, 2011Assignee: Mitsubishi Electric CorporationInventor: Hajime Akiyama
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Publication number: 20110281419Abstract: A method for manufacturing a dielectric isolation type semiconductor device comprises: forming a plurality of trenches in a first region on a major surface of a semiconductor substrate; forming a first dielectric layer on the major surface of the semiconductor substrate and a first thick dielectric layer in the first region by oxidizing a surface of the semiconductor substrate; bonding a semiconductor layer of a first conductive type to the semiconductor substrate via the first dielectric layer; forming a first semiconductor region by implanting an impurity into a part of the semiconductor layer above the first thick dielectric layer; forming a second semiconductor region by implanting an impurity of a second conductive type into a part of the semiconductor layer so as to surround the first semiconductor region separating from the first semiconductor region.Type: ApplicationFiled: December 3, 2010Publication date: November 17, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Hajime AKIYAMA
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Publication number: 20110254049Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.Type: ApplicationFiled: June 14, 2011Publication date: October 20, 2011Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Kazuhiro SHIMIZU, Hajime AKIYAMA, Naoki YASUDA
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Patent number: 7977787Abstract: A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.Type: GrantFiled: December 11, 2008Date of Patent: July 12, 2011Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuhiro Shimizu, Hajime Akiyama, Naoki Yasuda