Abstract: A dielectric separation type semiconductor device having high voltage withstanding capability includes a primary dielectric layer (3-1) on a first surface of a semiconductor substrate (1), a first conductivity type first semiconductor layer (2) disposed oppositely to the substrate (1) with the primary dielectric layer (3-1) sandwiched, a first conductivity type second semiconductor layer (4) on the first semiconductor layer (2), a second conductivity type third semiconductor layer (5) surrounding peripherally the first semiconductor layer (2), a ring-like insulation film (9) surrounding peripherally the third semiconductor layer (5), a first electrode (6) on the second semiconductor layer (4), a second electrode (7) on the third semiconductor layer (5), a back-surface electrode (8) deposited on a second surface of the substrate (1), and a first auxiliary dielectric layer (3-2) disposed immediately below the second semiconductor layer (4), being junctioned to the second surface.

Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p+-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p+-type impurity region (33) and the PMOS (15), an n+-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n+-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).

Abstract: A dielectric isolation type semiconductor device can achieve high dielectric resistance while preventing the dielectric strength thereof from being limited depending on the thickness of a dielectric layer and the thickness of a first semiconductor layer. A drift N? region is bonded to a semiconductor substrate through a buried oxide film to from a high withstand-voltage device in the drift N? region. A first field plate is formed on the drift N? region in the vicinity of a drain electrode. A first high silicon concentration region composed of a buried N+ region is formed in a porous oxide film region forming a part of the buried oxide film at a location right under the drain electrode. The drain electrode and the first field plate are electrically connected to the first high silicon concentration region through a drain N? well region.

Abstract: A dielectric isolation type semiconductor device and a manufacturing method therefor achieve high dielectric resistance while preventing the dielectric strength of the semiconductor device from being limited depending on the thickness of a dielectric layer and the thickness of a first semiconductor layer. A semiconductor substrate (1) and an n? type semiconductor layer (2) are bonded to each other through a buried oxide film layer (3). A first porous oxide film area (10) is formed in the semiconductor substrate in a state contacting with the buried oxide film layer. A power device is formed on the n? type semiconductor layer. The first porous oxide film area is formed in an area including a location right under a first main electrode (6) and extending from the first main electrode side up to a range of more than 40% of a distance (L) between the first and second main electrodes (6, 7).

Abstract: A semiconductor device is provided which is capable of avoiding malfunction and latchup breakdown resulting from negative variation of high-voltage-side floating offset voltage (VS). In the upper surface of an n-type impurity region (28), a p+-type impurity region (33) is formed between an NMOS (14) and a PMOS (15) and in contact with a p-type well (29). An electrode (41) resides on the p+-type impurity region (33) and the electrode (41) is connected to a high-voltage-side floating offset voltage (VS). The p+-type impurity region (33) has a higher impurity concentration than the p-type well (29) and is shallower than the p-type well (29). Between the p+-type impurity region (33) and the PMOS (15), an n+-type impurity region (32) is formed in the upper surface of the n-type impurity region (28). An electrode (40) resides on the n+-type impurity region (32) and the electrode (40) is connected to a high-voltage-side floating supply absolute voltage (VB).

Abstract: A dielectric separation type semiconductor device of high voltage withstanding capability includes a primary dielectric layer (3-1) on a first surface of a semiconductor substrate (1), a first semiconductor layer (2) of first conductivity type disposed oppositely to the substrate (1) with the primary dielectric layer (3-1) sandwiched, a second semiconductor layer (4) of first conductivity type on the first semiconductor layer (2), a third semiconductor layer (5) of second conductivity type surrounding peripherally the first semiconductor layer (2), a ring-like insulation film (9) surrounding peripherally the third semiconductor layer (5), a first electrode (6) on the second semiconductor layer (4), a second electrode (7) on the third semiconductor layer (5), a back-surface electrode (8) deposited on a second surface of the substrate (1), and a first auxiliary dielectric layer (3-2) disposed immediately below the second semiconductor layer (4), being junctioned to the second surface.

Abstract: Provided is a DAD that improves resistance to latch-up and stabilizes breakdown voltage characteristic. Specifically, a first gate electrode (10) and a second drain electrode (13) are linear electrodes having a length not exceeding the length of a source electrode (9). An isolation region (20) is disposed on both end portions of these electrodes. The region surrounded by two isolation regions (20) and the source electrode (9) becomes a P channel MOS region (PR) where a P channel MOS transistor is to be formed. The isolation region (20) has a multi-trench structure that a plurality of trenches (21) are provided in a P type impurity region disposed so as to be rectangle as viewed in plan configuration. Each trench (21) is filled with a conductor such as polysilicon, and the filled conductor is disposed so that it makes no electrical contact with any specific part.

Abstract: A polyurethane foam which is obtained by reacting an addition-polymerizable active hydrogen component comprising a compound having a group containing active hydrogen and an addition-polymerizable functional group or comprising both this compound and a compound containing at least 2.5 groups (on the average) containing active hydrogen and not containing addition-polymerizable functional groups with an organic polyisocyanate in the presence or absence of at least one auxiliary selected from the group consisting of foaming agents and additives to polymerize the addition-polymerizable functional group and simultaneously form a polyurethane, and which has a structure in which the chains formed by the addition polymerization have been cross-linked to the polyurethane chains. The polyurethane foam is useful as a rigid polyurethane foam excellent in hardness, dimensional stability, etc. and usable as a heat insulator, shock-absorbing material, synthetic wood, etc.

Abstract: A polyurethane foam which is obtained by reacting an addition-polymerizable active hydrogen component comprising a compound having a group containing active hydrogen and an addition-polymerizable functional group or comprising both this compound and a compound containing at least 2.5 groups (on the average) containing active hydrogen and not containing addition-polymerizable functional groups with an organic polyisocyanate in the presence or absence of at least one auxiliary selected from the group consisting of foaming agents and additives to polymerize the addition-polymerizable functional group and simultaneously form a polyurethane, and which has a structure in which the chains formed by the addition polymerization have been cross-linked to the polyurethane chains. The polyurethane foam is useful as a rigid polyurethane foam excellent in hardness, dimensional stability, etc. and usable as a heat insulator, shock-absorbing material, synthetic wood, etc.

Abstract: Provided is a DAD that improves resistance to latch-up and stabilizes breakdown voltage characteristic. Specifically, a first gate electrode (10) and a second drain electrode (13) are linear electrodes having a length not exceeding the length of a source electrode (9). An isolation region (20) is disposed on both end portions of these electrodes. The region surrounded by two isolation regions (20) and the source electrode (9) becomes a P channel MOS region (PR) where a P channel MOS transistor is to be formed. The isolation region (20) has a multi-trench structure that a plurality of trenches (21) are provided in a P type impurity region disposed so as to be rectangle as viewed in plan configuration. Each trench (21) is filled with a conductor such as polysilicon, and the filled conductor is disposed so that it makes no electrical contact with any specific part.

Abstract: A diode having a p+ semiconductor region, an n− drift region and an n+ semiconductor region is formed in an SOI layer. An SiC layer is formed in the bottom surface of a semiconductor layer. Further, a capacitive coupled multiple field plate including conductive layers is formed between cathode and anode electrodes. As a result, a semiconductor device with a lateral high breakdown voltage element having extremely high breakdown voltage which is never restricted by electric field concentration in the surface of the SOI layer can be achieved.

Abstract: An isolation structure capable of preventing deterioration of breakdown voltage of a semiconductor device is obtained. The isolation structure, positioned between first and second conductive regions formed on a major surface of a semiconductor substrate for electrically insulating the first and second conductive regions from each other, includes a first conductor formed on a position deeper than the major surface of the semiconductor substrate, an insulator positioned in a direction opposite to that of the position of the first conductive region as viewed from the first conductor and formed on a position deeper than the major surface of the semiconductor substrate and a second conductor positioned in a direction opposite to that of the position of the first conductor as viewed from the insulator and formed on a position deeper than the major surface of the semiconductor substrate.

Abstract: A thyris a thyristor is provided in which a lifetime of a minority carrier is controlled to improve the trade-off relationship between an ON-state voltage and a turn-off time and attain a high frequency and a low loss. Shielding members formed of metal plates are provided respectively in spaces above a plane on which a cathode electrode is provided and a plane on which an anode electrode is provided.

Abstract: A semiconductor device includes a p channel MOS transistor with a p.sup.- diffusion region, a p.sup.+ diffusion region and a gate electrode formed on the main surface of an n.sup.- layer on a buried oxide film. The p.sup.- diffusion region includes a plurality of branch-like regions to be connected to a p.sup.+ diffusion region. A source electrode is formed at the p.sup.+ diffusion region. An n.sup.+ diffusion region is formed within the p.sup.+ diffusion region. A drain electrode is connected to the p.sup.+ diffusion region and the n.sup.+ diffusion region. According to this structure, the depletion layer between the source electrode and the drain electrode is expanded. A semiconductor device is achieved that is improved in the breakdown voltage at the time of an off operation, or that is improved in on driving current at the time of an on operation with improved breakdown voltage at the time of an off operation.

Abstract: An SOI semiconductor substrate of a semiconductor device includes an SOI layer, an embedded oxide film, a semiconductor substrate, an insulating layer, and a protective coat. The protective coat protects the insulating layer from an oxide film etchant in semiconductor manufacturing processes. The stress applied between the semiconductor substrate, embedded oxide film, and insulating layer is relaxed and restrained.

Abstract: An n.sup.- layer is formed on a main surface of a p-type semiconductor substrate. A p.sup.- diffusion region is formed at a surface of n.sup.- layer. A p diffusion region is formed contiguous to one end of p.sup.- diffusion region. A plurality of p diffusion regions containing p-type impurity the concentration of which is higher than that of p.sup.- diffusion region are formed in p.sup.- diffusion region. A p diffusion region is formed such that it is spaced apart from p.sup.- diffusion region. A gate electrode is formed on a surface of n.sup.- layer positioned between p diffusion region and p.sup.- diffusion region with an oxide film interposed. A drain electrode is formed in contact with a surface of p diffusion region. Furthermore, an n diffusion region is formed adjacent to p diffusion region, and a source electrode is formed in contact with both a surface of n diffusion region and a surface p diffusion region.

Abstract: An n.sup.- layer is formed on a main surface of a p-type semiconductor substrate. A p.sup.- diffusion region is formed at a surface of n.sup.- layer. A p diffusion region is formed contiguous to one end of p.sup.- diffusion region. A plurality of p diffusion regions containing p-type impurity the concentration of which is higher than that of p.sup.- diffusion region are formed in p.sup.- diffusion region. A p diffusion region is formed such that it is spaced apart from p.sup.- diffusion region. A gate electrode is formed on a surface of n.sup.- layer positioned between p diffusion region and p.sup.- diffusion region with an oxide film interposed. A drain electrode is formed in contact with a surface of p diffusion region. Furthermore, an n diffusion region is formed adjacent to p diffusion region, and a source electrode is formed in contact with both a surface of n diffusion region and a surface p diffusion region.

Abstract: In the present invention, baneful influences such as the reduction of the threshold voltage due to the irradiation of an ionizing radiation such as an electron beam and a light ion beam are removed to practice the lifetime control of an IGBT with good controllability. Basically, the lifetime control without change in the threshold voltage is implemented by increasing the threshold voltage on or before irradiating the ionizing radiation so as to cancel the influence of each other. Further, the lifetime control without change in the threshold voltage is implemented with higher accuracy by irradiating a light ion beam from a rear main electrode side so as to cause crystal defects locally in a specific region in an epitaxial layer.

Abstract: In the present invention, baneful influences such as the reduction of the threshold voltage due to the irradiation of an ionizing radiation such as an electron beam and a light ion beam are removed to practice the lifetime control of an IGBT with good controllability. Basically, the lifetime control without change in the threshold voltage is implemented by increasing the threshold voltage on or before irradiating the ionizing radiation so as to cancel the influence of each other. Further, the lifetime control without change in the threshold voltage is implemented with higher accuracy by irradiating a light ion beam from a rear main electrode side so as to cause crystal defects locally in a specific region in an epitaxial layer.

Abstract: An insulated gate bipolar transistor has a P-type well region which is partially formed in a surface of an N.sup.- -type epitaxial layer formd on a P.sup.+ -type semiconductor substrate. An N.sup.+ -type emitter region is partially formed in a surface of the well region. A buried emitter electrode is provided in a boundary portion between the well and the emitter region. The buried emitter electrode is electrically connected with a emitter electrode formed on the emitter region through a conductor layer formed in the emitter region. Thus, a parasitic working area of a parasitic transistor formed by the epitaxial layer, well region and emitter region is extremely reduced to effectively prevent a latch-up. Further, the effective area of the emitter electrode is increased to increase current capacity.