Abstract: An optical proximity correction (OPC) system and methods thereof are provided. The example OPC system may include an integrated circuit (IC) layout generation unit generating an IC layout, a database unit storing a first plurality of OPC models, each of the first plurality of OPC models associated with one of a plurality of target specific characteristics and a mask layout generation unit including a model selector selecting a second plurality of OPC models based on a comparison between the target specific characteristics associated with the plurality of OPC models and the generated IC layout, the mask layout generation unit generating a mask layout based on the IC layout and the selected second plurality of OPC models.

Abstract: Methods for manufacturing semiconductor devices with contact bodies extended in a direction of a bit line to increase the contact area between a contact body and a storage electrode is provided. In one aspect a method includes forming gate lines on a semiconductor substrate, forming a first insulating layer to cover the gate lines, forming first contact pads and second contact pads, which are electrically connected to the semiconductor substrate between the gate lines, by penetrating the first insulating layer. Further, a second insulating layer is formed to cover the first contact pads and the second contact pads, and bit lines are formed across over the gate lines and are electrically connected to the second contact pads by penetrating the second insulating layer. In addition, a third insulating layer is formed to cover the bit lines and is selectively etched to form a band-type opening that crosses the bit lines and exposes the first contact pads.

Abstract: A polymer, a top coating layer, a top coating composition and an immersion lithography process using the same are provided. The polymer used as a top coating layer covering (or formed on) a photoresist may include a specific chemical structure. The top coating composition may include a solvent and a polymer of having the specific chemical structure. The immersion lithography process includes forming a photoresist layer on a wafer, forming a top coating layer on the photoresist layer, immersing the wafer in water, performing an exposure process on the photoresist layer and forming a photoresist pattern by removing the top coating layer and the photoresist layer with a developer.

Abstract: A method for cleaning a substrate on which a silicon layer and a silicon germanium layer are formed and exposed, and method for fabricating a semiconductor device using the cleaning method are disclosed. The cleaning method comprises preparing a semiconductor substrate on which a silicon layer and a silicon germanium layer are formed and exposed; and performing a first cleaning sub-process that uses a first cleaning solution to remove a native oxide layer from the semiconductor substrate. The cleaning method further comprises performing a second cleaning sub-process on the semiconductor substrate after performing the first cleaning sub-process, wherein the second cleaning sub-process comprises using a second cleaning solution. In addition, the second cleaning solution comprises ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and deionized water (H2O), and the second cleaning solution comprises at least 200 times more deionized water (H2O) than ammonium hydroxide (NH4OH) by volume.

Abstract: Provided are example embodiments of the invention including a range of polymer structures suitable for incorporation in barrier compositions for use, for example, in immersion photolithography in combination with a suitable solvent or solvent system. These polymers exhibit a weight average molecular weight (Mw) of 5,000 to 200,000 daltons and may be generally represented by formula I: wherein the expressions (1+m+n)=1; 0.1?(1/(1+m+n))?0.7; 0.3?(m/(1+m+n))?0.9; and 0.0?(n/(1+m+n))?0.6 are satisfied; R1, R2 and R3 are C1 to C5 alkyl, C1 to C5 alkoxy and hydroxyl groups; and Z represents an alkene that includes at least one hydrophilic group. Barrier coating compositions will include an organic solvent or solvent system selected from C3 to C10 alcohol-based organic solvents, C4 to C12 alkane-based organic solvents and mixtures thereof.

Abstract: The semiconductor structure includes an etch target layer to be pattemed, a multiple bottom anti-reflective coating (BARC) layer, and a photoresist (PR) pattern. The multiple BARC layer includes a first mask layer formed on the etch target layer and containing carbon, and a second mask layer formed on the first mask layer and containing silicon. A PR layer formed on the multiple BARC layer undergoes photolithography to form the PR pattern on the multiple BARC layer. The multiple BARC layer has a reflectance of 2% or less, and an interface angle between the PR pattern and the multiple BARC layer is 80° to 90°.

Abstract: An optical mask for use with an exposure beam includes a mask substrate adapted to be placed on a traveling path of the exposure beam. A reference pattern is formed on the mask substrate. The reference pattern is adapted to direct the exposure beam to travel in a predetermined reference direction. A comparative pattern is formed on the mask substrate. The comparative pattern is adapted to direct the exposure beam to travel in a direction inclined at a predetermined angle with respect to the reference direction.

Abstract: The present invention provides a double photolithography method in which, after a first photoresist pattern including a crosslinkable agent is formed on a semiconductor substrate, a crosslinkage is formed in a molecular structure of the first photoresist pattern. A second photoresist film may be formed on a surface of the semiconductor substrate on which the crosslinked first photoresist patterns are formed. Second photoresist patterns may be formed by exposing, post-exposure baking, and developing the second photoresist film.

Abstract: A focus monitoring mask includes a transparent substrate, e.g., a quartz layer. A light blocking film, e.g., a chromium-containing film, is disposed on the transparent substrate and has an opening therein. A transparent unit is disposed in a portion of the substrate exposed by the opening. The transparent unit includes a first phase shifter, a second phase shifter and a third phase shifter arranged adjacently in order of amount of phase shift. The second phase shifter is configured to provide an about 180° phase difference with respect to the first phase shifter. The third phase shifter is configured to provide a phase difference other than about 0° and about 180° with respect to the first phase shifter. The transparent unit may further include a fourth phase shifter having a fourth phase difference with respect to the first phase shifter that differs from about 0°, about 180° and the phase difference provided by the third phase shifter.

Abstract: There are provided methods of performing a photolithography process for forming asymmetric semiconductor patterns and methods of forming a semiconductor device using the same. These methods provide a way of forming asymmetric semiconductor patterns on a photoresist layer through two exposure processes. To this end, a semiconductor substrate is prepared. A planarized insulating interlayer and a photoresist layer are sequentially formed on the overall surface of the semiconductor substrate. A first semiconductor pattern of a photolithography mask is transferred to the photoresist layer, thereby forming a photoresist pattern on the photoresist layer. A second semiconductor pattern of a second photolithography mask is continuously transferred to the photoresist layer, thereby forming a second photoresist pattern on the photoresist layer.

Abstract: A semiconductor memory device may include a substrate having a plurality of active regions and a field isolation layer on the substrate surrounding the active regions of the substrate. Each of the plurality of active regions may have a length in a direction of a first axis and a width in a direction of a second axis, and the length may be greater than the width. The plurality of active regions may be provided in a plurality of columns of active regions in the direction of the second axis, and active regions of adjacent columns may be offset in the direction of the second axis.

Abstract: A method of fabricating a semiconductor device includes forming a material layer on a substrate, forming a mask layer on the material layer, and implanting ions into the mask layer to reduce light absorption thereof. An alignment key may be formed between the material layer and the substrate, and a location of the alignment key may be optically determined through the implanted mask layer. The implanted mask layer is patterned to define a mask pattern, and the material layer is patterned using the mask pattern as an etching mask. Related devices are also discussed.

Abstract: DRAM devices include a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and intersecting the word lines. A plurality of active regions is provided that are electrically coupled to the word lines and the bit lines. Each of the active regions defines a single unit memory cell having an area of 6F2 in terms of a minimum line width F. Each of the active regions may be overlapped by only one word line and the active regions may be defined by an isolation region.

Abstract: There are provided a method of forming a trench for a recessed channel of a transistor and a layout for the same. A layout for the recessed channel according to one aspect of the present invention is formed such that an open region is extended across at least one of a first active region in a lateral direction, and also across another second active region in parallel with the first active region in a diagonal direction, and the extension is cut not to reach an isolation region between two third active regions that are in parallel with the second active region in a diagonal direction, and have noses facing each other in a longitudinal direction, and the layout includes an alignment of a plurality of open regions, which are discontinuously aligned. An etch mask is formed using the layout, and a semiconductor substrate is etched using the etch mask, and a trench for a recessed channel is formed on the active region.

Abstract: In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.

Abstract: A mask corrects for an optical proximity effect (OPE). A dummy pattern having a phase-edge effect is formed on a mask substrate. The phase-edge effect reduces the intensity of light at the boundary of two transmitting regions from through transmitted light has a phase difference. A pattern can then be formed in a photolithographic process using the phase-edge effect. A difference between “isolated” and “dense” patterns formed on a wafer can be reduced by forming a dummy pattern in an isolated pattern region of the mask and making the diffraction pattern of the isolated pattern the same as that of the dense pattern, thereby improving the total focus margin. Because the intensity of light is reduced at the boundary between a first region in which the phase of the transmitted light is 0° and a second region in which the phase of the transmitted light is 180°, for example, a photoresist layer is not photosensitized.

Abstract: A mask corrects for an optical proximity effect (OPE). A dummy pattern having a phase-edge effect is formed on a mask substrate. The phase-edge effect reduces the intensity of light boundary of two transmitting regions from through transmitted light has a phase difference. A pattern can then be formed in a photolithographic process using the phase-edge effect. A difference between “isolated” and “dense” patterns formed on a wafer can be reduced by forming a dummy pattern in a isolated pattern region of the mask and making the diffraction pattern of the isolated pattern the same as that of the dense pattern, thereby improving the total focus margin. Because the intensity of light is reduced at the boundary between a first region in which the phase of the transmitted light is 0° and a second region in which the phase of the transmitted light is 180°, for example, a photoresist layer is not photosensitized.

Abstract: Methods for manufacturing semiconductor devices with contact bodies extended in a direction of a bit line to increase the contact area between a contact body and a storage electrode is provided. In one aspect a method includes forming gate lines on a semiconductor substrate, forming a first insulating layer to cover the gate lines, forming first contact pads and second contact pads, which are electrically connected to the semiconductor substrate between the gate lines, by penetrating the first insulating layer. Further, a second insulating layer is formed to cover the first contact pads and the second contact pads, and bit lines are formed across over the gate lines and are electrically connected to the second contact pads by penetrating the second insulating layer. In addition, a third insulating layer is formed to cover the bit lines and is selectively etched to form a band-type opening that crosses the bit lines and exposes the first contact pads.

Abstract: A semiconductor device including an anti-reflective cap and spacer, a method of manufacturing the same, and a method of forming a photoresist pattern using the same are provided. The semiconductor device according to the present invention includes an anti-reflective cap and an anti-reflective spacer on an upper surface and side walls of a reflective pattern formed on the semiconductor substrate. Therefore, the deformation of the photoresist pattern by the light reflected from the reflective pattern is minimized during a photolithography process.

Abstract: A mask corrects for an optical proximity effect (OPE). A dummy pattern having a phase-edge effect is formed on a mask substrate. The phase-edge effect reduces the intensity of light boundary of two transmitting regions from through transmitted light has a phase difference. A pattern can then be formed in a photolithographic process using the phase-edge effect. A difference between “isolated” and “dense” patterns formed on a wafer can be reduced by forming a dummy pattern in a isolated pattern region of the mask and making the diffraction pattern of the isolated pattern the same as that of the dense pattern, thereby improving the total focus margin. Because the intensity of light is reduced at the boundary between a first region in which the phase of the transmitted light is 0° and a second region in which the phase of the transmitted light is 180°, for example, a photoresist layer is not photosensitized.