Patents by Inventor Han-Mei Choi
Han-Mei Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8970039Abstract: A semiconductor device includes a plurality of electrode structures perpendicularly extending on a substrate, and at least one support unit extending between the plurality of electrode structures. The support unit includes at least one support layer including a noncrystalline metal oxide contacting a part of the plurality of electrode structures. Related devices and fabrication methods are also discussed.Type: GrantFiled: December 6, 2012Date of Patent: March 3, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Bong-jin Kuh, Sang-ryol Yang, Soon-wook Jung, Young-sub You, Byung-hong Chung, Han-mei Choi, Jong-sung Lim
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Publication number: 20140377926Abstract: A fin type active pattern is formed on a substrate. The fin type active pattern projects from the substrate. A diffusion film is formed on the fin type active pattern. The diffusion film includes an impurity. The impurity is diffused into a lower portion of the fin type active pattern to form a punch-through stopper diffusion layer.Type: ApplicationFiled: June 3, 2014Publication date: December 25, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Gon KIM, Jong-Hoon Kang, Eun-Young Jo, Gil-Heyun Choi, Han-Mei Choi
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Publication number: 20140357062Abstract: A method of fabricating a semiconductor device, the method including forming a trench on a substrate; forming an insulating layer pattern within the trench; depositing an amorphous material on the substrate and the insulating layer pattern; planarizing the amorphous material; removing a portion of the amorphous material, the removed portion of the amorphous material being on an area of the substrate where the trench has been formed; crystallizing remaining portions of the amorphous material into a single crystal material; and planarizing the single crystal material.Type: ApplicationFiled: May 29, 2014Publication date: December 4, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Joong-Han SHIN, Bong-Jin KUH, Tae-Gon KIM, Han-Mei CHOI, Jeong-Meung KIM
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Publication number: 20140357071Abstract: A method of manufacturing a semiconductor device having a doped layer may be provided. The method includes providing a substrate having a first region and a second region, forming a gate dielectric layer on the substrate, forming a first gate electrode layer on the gate dielectric layer, forming a first doped layer on the first gate electrode layer, forming a first capping layer on the first doped layer, forming a mask pattern on the first capping layer in the first region, the mask pattern exposing the first capping layer in the second region, removing the first capping layer and the first doped layer in the second region, removing the mask pattern, and forming a second doped layer on the first capping layer in the first region and the first gate electrode layer in the second region.Type: ApplicationFiled: May 13, 2014Publication date: December 4, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eun-Young JO, Jong-Hoon KANG, Tae-Gon KIM, Han-Mei CHOI
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Patent number: 8883608Abstract: An alignment mark is formed on a substrate including a first region and a second region. The alignment mark is formed in the second region. An etch target layer including a crystalline material is formed on the alignment mark and the substrate. The etch target layer in the first region is partially amorphized. The amorphized etch target layer is etched to form an opening.Type: GrantFiled: May 15, 2013Date of Patent: November 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hoon Kang, Tae-Gon Kim, Han-Mei Choi, Eun-Young Jo
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Publication number: 20140322832Abstract: According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster.Type: ApplicationFiled: December 9, 2013Publication date: October 30, 2014Inventors: Tae-Gon KIM, Jong-Hoon KANG, Jae-Young AHN, Jun-Kyu YANG, Han-Mei CHOI, Ki-Hyun HWANG
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Publication number: 20140256117Abstract: A method of forming an epitaxial layer includes forming a plurality of first insulation patterns in a substrate, the plurality of first insulation patterns spaced apart from each other, forming first epitaxial patterns on the plurality of first insulation patterns, forming second insulation patterns between the plurality of first insulation patterns to contact the plurality of first insulation patterns, and forming second epitaxial patterns on the second insulation patterns and between the first epitaxial patterns to contact the first epitaxial patterns, the first epitaxial patterns and the second epitaxial patterns forming a single epitaxial layer.Type: ApplicationFiled: December 19, 2013Publication date: September 11, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Joong-han SHIN, Bong-jin KUH, Ki-chul KIM, Jeong-meung KIM, Eun-ha LEE, Jong-sung LIM, Han-mei CHOI
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Patent number: 8822287Abstract: Methods of manufacturing semiconductor devices include forming an integrated structure and a first stopping layer pattern in a first region. A first insulating interlayer and a second stopping layer are formed. A second preliminary insulating interlayer is formed by partially etching the second stopping layer and the first insulating interlayer in the first region. A first polishing is performed to remove a protruding portion. A second polishing is performed to expose the first and second stopping layer patterns.Type: GrantFiled: December 7, 2011Date of Patent: September 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Hyo-Jung Kim, Ki-hyun Hwang, Kyung-Hyun Kim, Han-Mei Choi, Dong-Chul Yoo, Chan-Jin Park, Jong-Heun Lim, Myung-Jung Pyo, Byoung-Moon Yoon, Chang-Sup Mun
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Patent number: 8815697Abstract: Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer.Type: GrantFiled: May 23, 2012Date of Patent: August 26, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-Ho Yoon, Bong-Jin Kuh, Ki-Chul Kim, Gyung-Jin Min, Tae-Jin Park, Sang-Ryol Yang, Jung-Min Oh, Sang-Yoon Woo, Young-Sub Yoo, Ji-Eun Lee, Jong-Sung Lim, Yong-Moon Jang, Han-Mei Choi, Je-Woo Han
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Publication number: 20140209858Abstract: A nano-structure semiconductor light emitting device includes a base layer formed of a first conductivity type semiconductor, and a first insulating layer disposed on the base layer and having a plurality of first openings exposing partial regions of the base layer. A plurality of nanocores is disposed in the exposed regions of the base layer and formed of the first conductivity-type semiconductor. An active layer is disposed on surfaces of the plurality of nanocores and positioned above the first insulating layer. A second insulating layer is disposed on the first insulating layer and has a plurality of second openings surrounding the plurality of nanocores and the active layer disposed on the surfaces of the plurality of nanocores. A second conductivity-type semiconductor layer is disposed on the surface of the active layer positioned to be above the second insulating layer.Type: ApplicationFiled: January 27, 2014Publication date: July 31, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Nam Goo Cha, Bong Jin Kuh, Han Mei Choi
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Patent number: 8748249Abstract: A vertical structure non-volatile memory device in which a gate dielectric layer is prevented from protruding toward a substrate; a resistance of a ground selection line (GSL) electrode is reduced so that the non-volatile memory device is highly integrated and has improved reliability, and a method of manufacturing the same are provided. The method includes: sequentially forming a polysilicon layer and an insulating layer on a silicon substrate; forming a gate dielectric layer and a channel layer through the polysilicon layer and the insulating layer, the gate dielectric layer and the channel layer extending in a direction perpendicular to the silicon substrate; forming an opening for exposing the silicon substrate, through the insulating layer and the polysilicon layer; removing the polysilicon layer exposed through the opening, by using a halogen-containing reaction gas at a predetermined temperature; and filling a metallic layer in the space formed by removing the polysilicon layer.Type: GrantFiled: April 26, 2012Date of Patent: June 10, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-kyu Yang, Ki-hyun Hwang, Phil-ouk Nam, Jae-young Ahn, Han-mei Choi, Dong-chul Yoo
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Patent number: 8735247Abstract: A method for fabricating a nonvolatile memory device is disclosed. The method includes forming a first structure for a common source line on a semiconductor substrate, the first structure extending along a first direction, forming a mold structure by alternately stacking a plurality of sacrificial layers and a plurality of insulating layers on the semiconductor substrate, forming a plurality of openings in the mold structure exposing a portion of the first structure, and forming a first memory cell string at a first side of the first structure and a second memory cell string at a second, opposite side of the first structure. The plurality of openings include a first through-hole and a second through-hole, each through-hole passing through the plurality of sacrificial layers and plurality of insulating layers, and the first through-hole and the second through-hole overlap each other in the first direction.Type: GrantFiled: August 5, 2011Date of Patent: May 27, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Chul Yoo, Ki-Hyun Hwang, Han-Mei Choi, Jin-Gyun Kim
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Publication number: 20140065793Abstract: An alignment mark is formed on a substrate including a first region and a second region. The alignment mark is formed in the second region. An etch target layer including a crystalline material is formed on the alignment mark and the substrate. The etch target layer in the first region is partially amorphized. The amorphized etch target layer is etched to form an opening.Type: ApplicationFiled: May 15, 2013Publication date: March 6, 2014Applicant: Samsung Electronics Co., Ltd.Inventors: Jong-Hoon Kang, Tae-Gon Kim, Han-Mei Choi, Eun-Young Jo
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Patent number: 8642458Abstract: A method of fabricating a nonvolatile memory device includes providing an intermediate structure in which a floating gate and an isolation film are disposed adjacent to each other on a semiconductor substrate and a gate insulating film is disposed on the floating gate and the isolation film, forming a conductive film on the gate insulating film, and annealing the conductive film so that part of the conductive film on an upper portion of the floating gate flows down onto a lower portion of the floating gate and an upper portion of the isolation film.Type: GrantFiled: March 7, 2012Date of Patent: February 4, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Byung-Hong Chung, Young-Hee Kim, In-Sun Yi, Han-Mei Choi
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Patent number: 8637917Abstract: An insulating pattern is disposed on a surface of a semiconductor substrate and includes a silicon oxynitride film. A conductive pattern is disposed on the insulating pattern. A data storage pattern and a vertical channel pattern are disposed within a channel hole formed to vertically penetrate the insulating pattern and the conductive pattern. The data storage pattern and the vertical channel pattern are conformally stacked along sidewalls of the insulating pattern and the conductive pattern. A concave portion is formed in the semiconductor substrate adjacent to the insulating pattern. The concave portion is recessed relative to a bottom surface of the insulating pattern.Type: GrantFiled: August 12, 2011Date of Patent: January 28, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Ju-Yul Lee, Han-Mei Choi, Dong-Chul Yoo, Young-Jong Je, Ki-Hyun Hwang
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Patent number: 8617947Abstract: A method of manufacturing a semiconductor device includes forming a channel region, forming a buffer layer on the channel region, and heat-treating the channel region by using a gas containing halogen atoms.Type: GrantFiled: April 26, 2012Date of Patent: December 31, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jun-kyu Yang, Phil-ouk Nam, Ki-hyun Hwang, Jae-young Ahn, Han-mei Choi, Bi-o Kim
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Patent number: 8497142Abstract: Methods of forming conductive patterns include forming a conductive layer including a metal element on a substrate. The conductive layer is partially etched to generate a residue including an oxide of the metal element and to form a plurality of separately formed conductive layer patterns. A cleaning gas is inflowed onto the substrate including the conductive layer pattern. The metal compound is evaporated to remove the metal element contained in the residue and to form an insulating interface layer on the conductive layer pattern and a surface portion of the substrate through a reaction of a portion of the cleaning gas and oxygen. The residue may be removed from the conductive layer pattern to suppress generation of a leakage current.Type: GrantFiled: May 6, 2011Date of Patent: July 30, 2013Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Jun-Kyu Yang, Young-Geun Park, Ki-Hyun Hwang, Han-Mei Choi, Dong-Chul Yoo
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Patent number: 8492251Abstract: A thin layer structure includes a substrate, a blocking pattern that exposes part of an upper surface of the substrate, and a single crystalline semiconductor layer on the part of the upper surface of the substrate exposed by the pattern and in which all outer surfaces of the single crystalline semiconductor layer have a <100> crystallographic orientation. The thin layer structure is formed by an SEG process in which the temperature is controlled to prevent migration of atoms in directions towards the central portion of the upper surface of the substrate. Thus, sidewall surfaces of the layer will not be constituted by facets.Type: GrantFiled: August 28, 2012Date of Patent: July 23, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Hoon Kang, Bong-Jin Kuh, Tae-Gon Kim, Han-Mei Choi, Ki-Chul Kim, Eun-Young Jo
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Patent number: 8440527Abstract: A memory device and a method of fabricating the same are provided. The memory device includes a tunneling dielectric layer on a substrate, a charge storage layer on the tunneling dielectric layer, a blocking dielectric layer on the charge storage layer, the blocking dielectric layer including a first dielectric layer having silicon oxide, a second dielectric layer on the first dielectric layer and having aluminum silicate, and a third dielectric layer formed on the second dielectric layer and having aluminum oxide, and an upper electrode on the blocking dielectric layer.Type: GrantFiled: March 5, 2010Date of Patent: May 14, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-Chul Yoo, Eun-Ha Lee, Hyung-Ik Lee, Ki-Hyun Hwang, Sung Heo, Han-Mei Choi, Yong-Koo Kyoung, Byong-Ju Kim
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Publication number: 20130115760Abstract: A thin layer structure includes a substrate, a blocking pattern that exposes part of an upper surface of the substrate, and a single crystalline semiconductor layer on the part of the upper surface of the substrate exposed by the pattern and in which all outer surfaces of the single crystalline semiconductor layer have a <100> crystallographic orientation. The thin layer structure is formed by an SEG process in which the temperature is controlled to prevent migration of atoms in directions towards the central portion of the upper surface of the substrate. Thus, sidewall surfaces of the layer will not be constituted by facets.Type: ApplicationFiled: August 28, 2012Publication date: May 9, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: JONG-HOON KANG, BONG-JIN KUH, TAE-GON KIM, HAN-MEI CHOI, KI-CHUL KIM, EUN-YOUNG JO