Abstract: An information collection method and apparatus retrieves, stores, and interactively displays block-oriented text and image information from broadcasting television video, by analyzing the information screen images from the video source providers on selected channels, with the unilateral processing at the viewer end alone. Also, the present invention provides a method for the video source providers to supply additional information with special image patterns in selected screen areas.

Abstract: A method of manufacturing a microelectronic device including, in one embodiment, providing a substrate having a plurality of partially completed microelectronic devices including at least one partially completed memory device and at least one partially completed transistor. At least a portion of the partially completed transistor is protected by forming a first layer over the portion of the partially completed transistor to be protected during a subsequent material removal step. A second layer is formed substantially covering the partially completed memory device and the partially completed transistor. Portions of the second layer are removed leaving a portion of the second layer over the partially completed memory device. At least a substantial portion of the first layer is removed from the partially completed transistor after the portions of the second layer are removed.

Abstract: A method is provided for forming a flash memory cell having an amorphous silicon floating gate capped by a CVD oxide, and a control gate formed over an intergate oxide layer formed over the oxide cap. Amorphous silicon is first formed over a gate oxide layer over a substrate, followed by the forming of a silicon nitride layer over the amorphous silicon layer. Silicon nitride is patterned to have a tapered opening so that the process window for aligning the floating gate with the active region of the cell is achieved with a relatively wide margin. Next, an oxide cap is formed over the floating gate. Using an oxide deposition method in place of the conventional polyoxidation method provides a less bulbous oxide formation over the floating gate, thus, yielding improved erase speed for the cell. The invention is also directed to a flash memory cell fabricated by the disclosed method.

Abstract: A process for forming a high voltage oxide (HV) and a select gate poly for a split-gate flash memory is disclosed. The general difficulty of forming oxides of two different thicknesses for two different areas on the same substrate is alleviated by forming an HV oxide layer over the entire substrate just prior to the forming of the control gate of a cell area after the forming of a gate oxide layer over the peripheral area of the substrate. At an immediate subsequent step, a peripheral gate is formed over the HV oxide over the peripheral area, and, as a final step, the forming of the control gate, or the select gate of the cell area follows next.

Abstract: A method to suppress bit-line leakage in a nonvolatile memory cell is achieved. The method comprises providing an array of nonvolatile memory cells comprising source and bulk terminals. The array comprises a plurality of subarrays. The sources of all the nonvolatile cells in each subarray are coupled together to form a common subarray source. Bulks of all the nonvolatile cells in the array are coupled together to form a common array bulk. A first, non-zero voltage is forced between the common subarray source and the common array bulk for a first subarray that is selected for an access operation. A second, non-zero voltage is forced between the common subarray source and the common array bulk for a second subarray that is not selected for an access operation. The second, non-zero voltage inhibits bit line leakage in the second subarray.

Abstract: A method and apparatus retrieves and interactively displays program guide information by analyzing the program information screen images from the video source provider on a dedicated service channel; with the unilateral processing at the viewer end alone. Also, the present invention provides a method to supply additional program information with special image patterns in selected screen areas. The present invention further provides the ability for the viewer to select programs for future viewing or recording.

Abstract: A method and apparatus performs testing, sorting, and packaging of partially defective semiconductor memory devices in order to construct usable memory chip or module packages that meet the specification of a fully or partially functional package.

Abstract: A method to suppress bit-line leakage in a nonvolatile memory cell is achieved. The method comprises providing an array of nonvolatile memory cells comprising source and bulk terminals. The array comprises a plurality of subarrays. The sources of all the nonvolatile cells in each subarray are coupled together to form a common subarray source. Bulks of all the nonvolatile cells in the array are coupled together to form a common array bulk. A first, non-zero voltage is forced between the common subarray source and the common array bulk for a first subarray that is selected for an access operation. A second, non-zero voltage is forced between the common subarray source and the common array bulk for a second subarray that is not selected for an access operation. The second, non-zero voltage inhibits bit line leakage in the second subarray.

Abstract: A method and apparatus controls the memory data access of memory devices in order to utilize partially defective memory devices to construct usable memory chip or module assemblies that meet the specification of a fully or partially functional assembly.

Abstract: A method and apparatus provides resistor network packages with some of the resistor sub-package positions remain open, which may accommodate different circuit configurations with a common circuit assembly. Also, the present invention provides a packaging method using resistor network packages as connecting and disconnecting mechanisms for the signal lines on the package.

Abstract: A method of etch polysilicon adjacent to a recessed STI structure feature is described. A substrate is provided with a dielectric layer thereon and a polysilicon layer on the dielectric layer. A shallow trench is formed that extends through the polysilicon and dielectric layers into the substrate. An insulating material is used to fill the trench and is then recessed in the trench below the surface of the substrate by polishing and etching steps. A conformal buffer layer is deposited which covers the polysilicon and sidewalls of the trench above the recessed insulating layer. The buffer layer is etched back to expose the insulating layer and the polysilicon is removed by a plasma etch. A spacer comprised of a portion of the buffer layer protects the substrate during the polysilicon etch to prevent unwanted trenches from being formed adjacent to the STI structure, thereby increasing the etch process window.

Abstract: A method and apparatus provides resistor networks with two or more resistance values, which may accommodate different circuit configurations with a common circuit assembly. Also, the present invention provides a packaging method using multiple-value resistor networks as connecting and disconnecting mechanisms for the signal lines on the package.

Abstract: A method is provided for forming a flash memory cell having an amorphous silicon floating gate capped by a CVD oxide, and a control gate formed over an intergate oxide layer formed over the oxide cap. Amorphous silicon is first formed over a gate oxide layer over a substrate, followed by the forming of a silicon nitride layer over the amorphous silicon layer. Silicon nitride is patterned to have a tapered opening so that the process window for aligning the floating gate with the active region of the cell is achieved with a relatively wide margin. Next, an oxide cap is formed over the floating gate. Using an oxide deposition method in place of the conventional polyoxidation method provides a less bulbous oxide formation over the floating gate, thus, yielding improved erase speed for the cell. The invention is also directed to a flash memory cell fabricated by the disclosed method.

Abstract: A method for forming square polysilicon spacers on a split gate flash memory device by a multi-step polysilicon etch process is described. The method can be carried out by depositing a polysilicon layer on the flash memory device structure and then depositing a sacrificial layer, such as silicon oxide, on top of the polysilicon layer. The sacrificial layer has a slower etch rate than the polysilicon layer during a main etch step. The sacrificial layer overlies the flash memory device is then removed, while the sacrificial layer on the sidewall is kept intact. The polysilicon layer that overlies the flash memory device is then etched away followed by a step of removing all residual sacrificial layers. The exposed polysilicon layer is then etched to define the square polysilicon spacers on the split gate flash memory device.

Abstract: A method and apparatus performs memory read and write operations according to a standard flash memory interface using more cost-effective DRAM devices while maintaining the non-volatile characteristics of a flash memory device using a standby power source. Also, the present invention provides a method that replaces defective memory cell locations with functional memory cell locations.

Abstract: A method and apparatus controls the read and write accesses of multi-level memory devices, chips, or modules in order to speed up the memory data transfer rate between a processing device and a memory device to increase the utilization of the data width of the memory cell array. Also, the present invention provides a method that is compatible with the structure of existing memory chips and modules.

Abstract: A method and apparatus performs testing, sorting, and packaging of partially defective semiconductor memory devices in order to construct usable memory chip or module packages that meet the specification of a fully or partially functional package.

Abstract: Within a method for fabricating a split gate field effect transistor (FET) within a semiconductor integrated circuit microelectronic fabrication there is employed a patterned mask layer as an etch mask layer for forming from a blanket floating gate electrode material layer a floating gate electrode. At least a portion of the patterned mask layer is then laterally etched to completely expose an edge of the floating gate electrode prior to forming over the floating gate electrode and the edge of the floating gate electrode an inter-gate electrode dielectric layer having formed thereupon a control gate electrode. The method contemplates a split gate field effect transistor (FET) device fabricated in accord with the method. The resulting split gate field effect transistor (FET) device has an enhanced control gate electrode to floating gate electrode registration.

Abstract: A method and apparatus controls the read-write accesses of a memory module, monitors the memory module status, generates module control signals, and arbitrates the read-write operations for a non-volatile memory that stores the memory characteristics, status, and control information.

Abstract: A method and apparatus controls the telephone call announcement and response according to the caller identification or caller-waiting identification, said announcement includes an audible sound such as a music sequence, a ringing signal, a voice segment, or a combination of sounds, some of which may contain caller description, caller group description, or called party description.