Abstract: A method and apparatus controls the memory data access of memory devices in order to utilize partially defective memory devices to construct usable memory chip or module assemblies that meet the specification of a fully or partially functional assembly.

Abstract: Within a method for fabricating a split gate field effect transistor (FET) within a semiconductor integrated circuit microelectronic fabrication there is employed a patterned mask layer as an etch mask layer for forming from a blanket floating gate electrode material layer a floating gate electrode. At least a portion of the patterned mask layer is then laterally etched to completely expose an edge of the floating gate electrode prior to forming over the floating gate electrode and the edge of the floating gate electrode an inter-gate electrode dielectric layer having formed thereupon a control gate electrode. The method contemplates a split gate field effect transistor (FET) device fabricated in accord with the method. The resulting split gate field effect transistor (FET) device has an enhanced control gate electrode to floating gate electrode registration.

Abstract: A method is taught for forming a rectangular or near rectangular polysilicon sidewall structure, which can be used as an ultra narrow MOSFET gate electrode. The method employs the use a step on a sacrificial oxide against which the polysilicon sidewall is formed. An etch stop, such as a gate oxide is formed alongside the step. A polysilicon layer is deposited over the step followed by a silicon nitride layer. Next a flowable layer is deposited and cured. In a first embodiment the flowable layer is deposited to completely cover the polysilicon layer. Next the wafer is planarized to exposed the polysilicon layer over the high part of the step an to a level wherein the polysilicon/silicon nitride interface is driven away from the step to a distance which determines the final width of the final sidewall structure. The residual flowable layer is then removed and a silicon oxide hardmask is grown over the exposed polysilicon.

Abstract: A method and apparatus provides multi-level memory data input-output signals to speed up the memory data transfer rate between a memory controlling device and a memory device to increase the utilization of the data width of the memory cell array. Also, the present invention provides a method that is compatible with the structure of existing memory chips and modules.

Abstract: A method and apparatus configures the data bits of partially defective memory devices in order to construct usable memory chip or module packages that meet the specification of a fully or partially functional package.

Abstract: A method and apparatus controls the memory access of memory devices in order to utilize partially defective memory devices to construct usable memory chip or module packages that meet the specification of a fully or partially functional package.

Abstract: A method for increasing the thickness of field oxide layer is provided. At first, a layer of pad oxide and a layer of silicon nitride mask are defined on a semiconductor substrate, and then a field oxide layer, which isolates active device regions, is formed. After the layer of pad oxide and the layer of silicon nitride are removed, a layer of silicon oxide is formed overlying the field oxide layer. The mentioned silicon oxide layer can increase the thickness of field oxide layer for effectively isolating active device regions without enlarging Bird's Beak. The present invention can also effectively improve the Gate Coupling Ratio in a Flash EEPROM.

Abstract: A bipolar variable resistance device suitable for integrated circuit applications includes a silicon substrate, and a resistive layer covering the silicon substrate, the resistive layer being doped with impurities of a first polarity and of a second polarity. A dielectric layer covers the resistive layer. A conductive layer covers the dielectric layer. The device is used to change the resistance of the resistive layer by varying a control voltage applied to the conductive layer.