Abstract: A k-nearest neighbors associative memory includes: a clock counting type associative memory that holds R pieces of reference data and outputs, for each of the R pieces of reference data, a match signal that becomes active when a clock count corresponding to a distance between the reference data and given search data has been reached; and a k-nearest neighbors clustering circuit that, every time at least one of the R match signals output from the clock counting type associative memory becomes active, selects a piece of class data, out of R pieces of class data representing classes of the R pieces of reference data, corresponding to each of the at least one active match signal, until k match signals out of the R match signals become active, and determines a class having a largest number of pieces of data when the selected total k pieces of class data are classified.

Abstract: A k-nearest neighbors associative memory includes: a clock counting type associative memory that holds R pieces of reference data and outputs, for each of the R pieces of reference data, a match signal that becomes active when a clock count corresponding to a distance between the reference data and given search data has been reached; and a k-nearest neighbors clustering circuit that, every time at least one of the R match signals output from the clock counting type associative memory becomes active, selects a piece of class data, out of R pieces of class data representing classes of the R pieces of reference data, corresponding to each of the at least one active match signal, until k match signals out of the R match signals become active, and determines a class having a largest number of pieces of data when the selected total k pieces of class data are classified.

Abstract: An associative memory that can reduce search errors is provided. An associative memory includes R distance/time conversion circuits DT1 to DTR. The R distance/time conversion circuits DT1 to DTR each include a NAND circuit 40 and N bit stages 41 to 4k. The N bit stages 41 to 4k delay a signal from the NAND circuit 40 by longer delay time as the distance between reference data and search data is greater and oscillate the signal. Among R oscillation signals output from the distance/time conversion circuits DT1 to DTR, the earliest changing oscillation signal is detected as an oscillation signal for the Winner row.

Abstract: An associative memory capable of reducing erroneous searches is provided. A storage memory in the associative memory stores reference data. A comparator circuit receives externally applied search data and obtains the distance (for example, the Hamming distance) between the reference data and the search data. An oscillating circuit outputs a pulse signal with an oscillating frequency corresponding to the distance obtained by the comparator circuit. Similarly, the oscillating circuits output pulse signals with oscillating frequencies according to the distance between the reference data in corresponding storage circuits and the search data. A WTA circuit receives the pulse signals. Reference data stored in a storage circuit corresponding to an oscillating circuit that outputs a pulse signal with the highest frequency is determined as the most similar reference data (Winner) to the search data.

Abstract: An associative memory that can reduce search errors is provided. An associative memory includes R distance/time conversion circuits DT1 to DTR. The R distance/time conversion circuits DT1 to DTR each include a NAND circuit 40 and N bit stages 41 to 4k. The N bit stages 41 to 4k delay a signal from the NAND circuit 40 by longer delay time as the distance between reference data and search data is greater and oscillate the signal. Among R oscillation signals output from the distance/time conversion circuits DT1 to DTR, the earliest changing oscillation signal is detected as an oscillation signal for the Winner row.

Abstract: An offset removal circuit (10) includes a removal circuit (1) and a removal circuit (2). The removal circuit (1) digitally removes offset voltage from an input voltage Vin. The removal circuit (2) removes offset voltage, in an analog manner, from the voltage subjected to offset voltage removal by the removal circuit (1). Then, the removal circuit (2) outputs the voltage subjected to the offset voltage removal to a non-inverting input terminal of a differential amplifier (20).

Abstract: An associative memory capable of reducing erroneous searches is provided. A storage memory in the associative memory stores reference data. A comparator circuit receives externally applied search data and obtains the distance (for example, the Hamming distance) between the reference data and the search data. An oscillating circuit outputs a pulse signal with an oscillating frequency corresponding to the distance obtained by the comparator circuit. Similarly, the oscillating circuits output pulse signals with oscillating frequencies according to the distance between the reference data in corresponding storage circuits and the search data. A WTA circuit receives the pulse signals. Reference data stored in a storage circuit corresponding to an oscillating circuit that outputs a pulse signal with the highest frequency is determined as the most similar reference data (Winner) to the search data.

Abstract: Associative memories capable of outputting multiple reference data close to search data are provided. A memory array compares each of the multiple reference data with the search data in parallel and generates multiple comparison current signals representing the result of the comparison. A WLA converts the multiple comparison current signals into voltages. During the first cycle, the WLA detects the lowest voltage among the voltages as Winner and detects the remaining voltages as Loser. After the second cycle, based on feedback signals, the WLA detects all the voltages other than a voltage detected as Winner during the last preceding cycle, and detects the lowest voltage among the detected voltages as Winner and detects the remaining detected voltages as Loser. The WLA repeats these operations k times.

Abstract: A dividing unit divides respective symbol sequences of input data applied with zigzag scan and a run-length process into a plurality of subsets having similar frequencies of occurrence, depending on a difference in frequencies of occurrence. A table creating unit scans each subset and creates a Huffman coding table for each subset. A coding unit executes a process for performing Huffman coding on each subset by using the Huffman coding table created for the subset, for all of the subsets in the plurality of subsets.

Abstract: A pixel-value detecting circuit (1) detects RGB values of each pixel of an input image and outputs the detected RGB values to a connection weight determining circuit (2). When both of two adjacent pixels have achromatic color, the connection weight determining circuit (2) determines a first connection weight, which is a connection weight between the two pixels, by using only the RGB values. When one of the two pixels has achromatic color, the connection weight determining circuit (2) determines, as a connection weight, a second connection weight that is smaller than the first connection weight, by using the RGB values and saturations. When both of the two pixels have chromatic color, the connection weight determining circuit (2) determines, as a connection weight, a third connection weight that is greater than or equal to the first connection weight, by using the RGB values and hues.

Abstract: A pixel-value detecting circuit (1) detects RGB values of each pixel of an input image and outputs the detected RGB values to a connection weight determining circuit (2). When both of two adjacent pixels have achromatic color, the connection weight determining circuit (2) determines a first connection weight, which is a connection weight between the two pixels, by using only the RGB values. When one of the two pixels has achromatic color, the connection weight determining circuit (2) determines, as a connection weight, a second connection weight that is smaller than the first connection weight, by using the RGB values and saturations. When both of the two pixels have chromatic color, the connection weight determining circuit (2) determines, as a connection weight, a third connection weight that is greater than or equal to the first connection weight, by using the RGB values and hues.

Abstract: An offset removal circuit (10) includes a removal circuit (1) and a removal circuit (2). The removal circuit (1) digitally removes offset voltage from an input voltage Vin. The removal circuit (2) removes offset voltage, in an analog manner, from the voltage subjected to offset voltage removal by the removal circuit (1). Then, the removal circuit (2) outputs the voltage subjected to the offset voltage removal to a non-inverting input terminal of a differential amplifier (20).

Abstract: A dividing unit divides respective symbol sequences of input data applied with zigzag scan and a run-length process into a plurality of subsets having similar frequencies of occurrence, depending on a difference in frequencies of occurrence. A table creating unit scans each subset and creates a Huffman coding table for each subset. A coding unit executes a process for performing Huffman coding on each subset by using the Huffman coding table created for the subset, for all of the subsets in the plurality of subsets.

Abstract: A semiconductor device includes a decoder receiving first multiplier data of 3 bits indicating a multiplier to output a shift flag, an inversion flag, and an operation flag in accordance with Booth's algorithm, and a first partial product calculation unit receiving first multiplicand data of 2 bits indicating a multiplicand, a shift flag, an inversion flag, and an operation flag to select one of the higher order bit and lower order bit of the first multiplicand data based on the shift flag, invert or non-invert the selected bit based on the inversion flag, select one of the inverted or non-inverted data and data of a predetermined logic level based on the operation flag, and output the selected data as partial product data indicating the partial product of the first multiplier data and the first multiplicand data.

Abstract: An amplifier circuit according to the present invention includes a plurality of input nodes receiving a plurality of input voltages (VI1 to VIR), a plurality of differential amplifiers provided corresponding to the plurality of input nodes, each having one input which receives a voltage of the corresponding input node, and a control circuit generating a control voltage (CONTROL) that follows a minimum voltage or a maximum voltage of the plurality of input voltages (VI1 to VIR) from outputs of the plurality of differential amplifiers and supplying the generated control voltage (CONTROL) as a common value to the other inputs of the plurality of differential amplifiers.

Abstract: An amplifier circuit according to the present invention includes a plurality of input nodes receiving a plurality of input voltages (VI1 to VIR), a plurality of differential amplifiers provided corresponding to the plurality of input nodes, each having one input which receives a voltage of the corresponding input node, and a control circuit generating a control voltage (CONTROL) that follows a minimum voltage or a maximum voltage of the plurality of input voltages (VI1 to VIR) from outputs of the plurality of differential amplifiers and supplying the generated control voltage (CONTROL) as a common value to the other inputs of the plurality of differential amplifiers.

Abstract: A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.

Abstract: Associative memories capable of outputting multiple reference data close to search data are provided. A memory array compares each of the multiple reference data with the search data in parallel and generates multiple comparison current signals representing the result of the comparison. A WLA converts the multiple comparison current signals into voltages. During the first cycle, the WLA detects the lowest voltage among the voltages as Winner and detects the remaining voltages as Loser. After the second cycle, based on feedback signals, the WLA detects all the voltages other than a voltage detected as Winner during the last preceding cycle, and detects the lowest voltage among the detected voltages as Winner and detects the remaining detected voltages as Loser. The WLA repeats these operations k times.

Abstract: A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.

Abstract: Cells i corresponding to pixels are initialized into a non-excitation state, to calculate coupling weights Wik between the eight cells k adjacent to the cells i, thereby determining leader cells pi=1 based on calculation results. Next, one leader cell yet to be excited is selected as a self-excitable cell. The selected cell is put into the excitation state, the excitable cells are selected based on the coupling weights between the adjacent cells, and the selected cells are put into the excitation state. These operations are repeated until no excitable cell is detected any more and, if there no excitable cell is detected any more, inhibition processing is performed, thereby completing image segmentation of one region. These operations are repeated until there is no non-excited and non-inhibited leader cell any more, thereby pinpointing regions belonging to the same category from an input image and identifying them as an image segmentation regions.