Abstract: A plurality of reference words based on a second distance index that allows coding of a first distance index are registered in an associative memory core in advance. In a first pipeline stage, a retrieved word having a predetermined number of bits is extracted from input data in a predetermined clock cycle, and the retrieved word is coded with the second distance index and output to the core. In a second pipeline stage, the core searches for a reference word inhabiting the largest similarity with respect to the retrieved word (winner) obtained in the previous clock cycle. In a third pipeline stage, the core output result in the previous clock cycle is analyzed, one winner is determined on the basis of a specific priority, and an address indicating the location of the winner and the distance between the input data and the winner are coded and output.

Abstract: A shared memory includes a plurality of multi-port memories each having at least one port with a copybus-function, and at least one port accessible from the user side. At least one copybus is connected to one of the ports with the copybus-function. The shared memory copies contents of one of the multi-port memories, which has been changed by a writing operation from the user side, to other multi-port memories through at least one copybus.

Abstract: A self-adjusting winner lineup amplifier comprising signal control sections which level-control comparison signals (Ci) from word weighted comparators of a memory area, a self-adjusting distance amplifying section corresponding to the respective rows in the memory area which outputs the level-controlled comparison signals (Ci) as distance amplified signals (LAi), a feedback generating section which inputs a self-adjusting voltage (Fa) common to the distance amplifying sections, and a voltage follower which converts its input voltage (min{Ci}; a minimum value of Ci) into a feedback voltage (F) to supply the feedback voltage (F) in parallel and with strong driving current to the signal control sections, wherein amplification characteristics of the distance amplifying section are self-adjusted by a comparison signal (Cwin) of a winner row, and the signal control sections lead the comparison signal (Cwin) into the range of a maximum gain area of the distance amplifying section.

Abstract: A plurality of reference words based on a second distance index that allows coding of a first distance index are registered in an associative memory core in advance. In a first pipeline stage, a retrieved word having a predetermined number of bits is extracted from input data in a predetermined clock cycle, and the retrieved word is coded with the second distance index and output to the core. In a second pipeline stage, the core searches for a reference word inhabiting the largest similarity with respect to the retrieved word (winner) obtained in the previous clock cycle. In a third pipeline stage, the core output result in the previous clock cycle is analyzed, one winner is determined on the basis of a specific priority, and an address indicating the location of the winner and the distance between the input data and the winner are coded and output.

Abstract: A self-adjusting winner lineup amplifier comprising signal control sections which level-control comparison signals (Ci) from word weighted comparators of a memory area, a self-adjusting distance amplifying section corresponding to the respective rows in the memory area which outputs the level-controlled comparison signals (Ci) as distance amplified signals (LAi), a feedback generating section which inputs a self-adjusting voltage (Fa) common to the distance amplifying sections, and a voltage follower which converts its input voltage (min{Ci}; a minimum value of Ci) into a feedback voltage (F) to supply the feedback voltage (F) in parallel and with strong driving current to the signal control sections, wherein amplification characteristics of the distance amplifying section are self-adjusted by a comparison signal (Cwin) of a winner row, and the signal control sections lead the comparison signal (Cwin) into the range of a maximum gain area of the distance amplifying section.

Abstract: In a first surface of a semiconductor substrate, there is formed a step by etching. In the first surface of the substrate, there are also formed source and drain junction regions on respective sides of the step, and source and drain electrodes are formed on the source and drain regions, respectively. An oxide film having a thickness not larger than 10 nm is formed on the first surface of the substrate such that a corner structure corresponding to the step is formed in the oxide film. A gate is formed on the oxide film, a gate electrode is formed on the gate, and a substrate electrode is formed on a second surface of the substrate. Information is stored in the memory by a deep level capture of carriers injected and contained in the oxide film at the corner structure.

Abstract: The circuit handles access contentions in memories with a plurality of mutually independent, addressable I/O ports. There are provided two subcircuits, namely the so-called contention identification circuit and the so-called access inhibit circuit. The contention identification circuit identifies an access contention between two or more ports and generates a status signal. This status signal is communicated to the contention inhibit circuit. The contention inhibit circuit allocates a priority to each of the ports which are involved in the access contention. Based on the prioritization, the highest prioritized port is enabled, while the remaining ports are inhibited (temporarily disabled). The prioritization proceeds according to a predetermined algorithm. Two specific prioritization algorithms are given, namely a simple so-called PIH algorithm, in which the ports are hierarchically designated and a so-called “fair” IPIH algorithm.

Abstract: An address and data transfer circuit includes enable circuit for enabling a single-port memory in accordance with an access requirement from a corresponding port out of a plurality of external ports. An active address selecting circuit selects an address from the corresponding port and transfers the address to the single port memory responsive to activation of the enabling circuit. An active data selecting circuit selects a data from the corresponding port and transfers the data to or from the single port memory, responsive to activation of the enabling circuit.

Abstract: A static memory is constructed in a plurality of hierarchy levels. Beneficial realization possibilities are set forth with respect to the surface utilization for the drive and read-out circuits in the second hierarchy level which are especially critical. Memory cells that supply a strong cell signal are advantageously utilized so that a low expense is needed in the read circuit. By displacing periphery circuits into higher hierarchy levels, a short access time and a reduced surface requirement arise.

Abstract: Memory cells are disclosed that avoid the utilization of analog circuits in the memory peripheral circuits when they are utilized in static memory modules and that intended to enhance the disturbed reliability when confronted by technology modifications and parameter fluctuations. Write-in thereby occurs from a write data line via a write selection transistor and read-out occurs via a read selection transistor onto a read data line. A second inverter formed of two field effect transistors serves as a feedback element in order to statically maintain the cell information. Due to an implemented asymmetry in the dimensioning between the first and second inverters, the memory cell is significantly less susceptible to information loss upon read-out when compared to a heretofore known memory cell. A precharging of the read data line is not required with these memory cells.

Abstract: A read amplifier formed of a load component (L), a differential amplifier component (DIFF), a compensation transistor (N6), a switching transistor (P1) connected between a supply voltage (V.sub.DD) and the load component (L). The pre-loading potential of the read amplifier at its outputs LA, LA is about 2.5 volts. During the pre-loading phase, the two supply voltages (V.sub.DD, V.sub.22 =ground) are disconnected and the pre-loading potential is established by compensation of capacitances at the outputs LA, LA which results in an improved read amplifier.

Abstract: An arrangement for DPCM coding with high data rate. In a DPCM coder, wherein respective prediction values (s) are subtracted from digitized picture element signals (s), the difference signals that result represent the prediction error .DELTA. supplied to a circuit element for cutputting a quantization error (11) pertaining to a difference signal. In a following adder, quantization errors (q) are added to the prediction errors (.DELTA.), whereby the quantized prediction error (.DELTA.q) can be taken at the output of the following adder. For forming the reconstructed picture element signal (s.sub.R), the quantization error (q) is added to the current picture element signal (s) in a first adder and is supplied to a first subtraction means via a predictor.