Patents by Inventor Hao A. Chen

Hao A. Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11982301
    Abstract: A connecting assembly is applied to connect a first housing and a second housing. The connecting assembly includes a general connecting member, a connecting base, and a clamping member. The general connecting member connects to the first housing. The general connecting member includes an accommodating portion and at least one opening. The accommodating portion is located inside the general connecting member. The opening is disposed on a side wall of the general connecting member and communicates with the accommodating portion. The connecting base is disposed on the second housing. The connecting base includes a main body disposed in the accommodating portion. The clamping member includes a flat portion and at least one clamping portion. The clamping portion extends from one end of the flat portion toward the connecting base, and the clamping portion passes through the opening and presses against the main body of the connecting base.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: May 14, 2024
    Assignee: CHICONY ELECTRONICS CO., LTD.
    Inventor: Chia-Hao Chen
  • Patent number: 11984363
    Abstract: A semiconductor device includes a semiconductor substrate, a first epitaxial feature having a first semiconductor material over the semiconductor substrate, and a second epitaxial feature having a second semiconductor material over the semiconductor substrate. The second semiconductor material being different from the first semiconductor material. The semiconductor device further includes a first silicide layer on the first epitaxial feature, a second silicide layer on the second epitaxial feature, a metal layer on the first silicide layer, a first contact feature over the metal layer, and a second contact feature over the second silicide layer. A first number of layers between the first contact feature and the first epitaxial feature is greater than a second number of layers between the second contact feature and the second epitaxial feature.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
  • Patent number: 11985662
    Abstract: A user equipment (UE) includes one or more non-transitory computer-readable media containing computer-executable instructions embodied therein, and at least one processor coupled to the one or more non-transitory computer-readable media. The at least one processor configured to execute the computer-executable instructions to receive downlink control information (DCI) on a downlink (DL) channel of a non-terrestrial network (NTN), the DL channel reception ending in a first slot, and transmit an uplink (UL) transmission on a UL channel of the NTN in a second slot. The second slot is separate from the first slot by a timing offset, where a duration of the timing offset is dependent on a type of the UL transmission and a numerology of the UL transmission.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 14, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Chien-Chun Cheng, Chia-Hao Yu, Hung-Chen Chen, Chie-Ming Chou
  • Patent number: 11982909
    Abstract: A method for manufacturing a liquid crystal display panel and a liquid crystal display panel are provided. The method of manufacturing a liquid crystal display panel comprises the following steps: grinding the display device along a preset edge and removing the adhesive layer on a side of the preset edge away from a frame sealant, to obtain the liquid crystal display panel.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: May 14, 2024
    Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Hao Chen
  • Patent number: 11984486
    Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopants and a second dopant, and the second dopant comprises a group V material.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chen-Hao Chiang
  • Publication number: 20240153821
    Abstract: Provided are a package structure having stacked semiconductor dies with wavy sidewalls and a method of forming the same. The package structure includes: a first die and a second die bonded together; a first encapsulant laterally encapsulating the first die; and a second encapsulant laterally encapsulating the second die, wherein a second interface of the second die in contact with the second encapsulant is a wavy interface in a cross-sectional plane.
    Type: Application
    Filed: February 23, 2023
    Publication date: May 9, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Shien CHEN, Chi-Yen Lin, Hsu-Hsien Chen, Ting Hao Kuo, Chang-Ching Lin
  • Publication number: 20240155185
    Abstract: A channel hiatus correction method for an HDMI device is provided. A recovery code from scrambled data of the stream is obtained. A liner feedback shift register (LFSR) value of channels of the HDMI port is obtained based on the recovery code and the scrambled data of the stream. The stream is de-scrambled according to the LFSR value of the channels of the HDMI port. Video data is displayed according to the de-scrambled stream.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 9, 2024
    Inventors: Chia-Hao CHANG, You-Tsai JENG, Kai-Wen YEH, Yi-Cheng CHEN, Te-Chuan WANG, Kai-Wen CHENG, Chin-Lung LIN, Tai-Lai TUNG, Ko-Yin LAI
  • Publication number: 20240147927
    Abstract: Provided herein are systems and methods for enhancement of polyphenols, such as chlorogenic acids, chicoric acid, anthocyanins, and water-soluble quercetin derivatives, production in red lettuces. Also provided are transgenic lettuce for the production of polyphenols. Also provided are parts of such transgenic lettuces, such as seeds leaves, and extracts. The disclosure also provides methods of using the new lettuces and parts thereof for protection against viral/bacterial infection (i.e., by inhibiting activities of COVID-19 virus/enzymes) diabetes, cardiovascular diseases, memory and eyesight loss, inflammation, and cancer.
    Type: Application
    Filed: February 25, 2022
    Publication date: May 9, 2024
    Inventors: Hao Chen, Tiehan Zhao, Xiaohui Yao, Zaihui Zhang, Jun Yan
  • Publication number: 20240148280
    Abstract: An implantable micro-biosensor a substrate, a first electrode, a second electrode, a third electrode, and a chemical reagent layer. The first electrode is disposed on the substrate and used as a counter electrode. The second electrode is disposed on the substrate and spaced apart from the first electrode. The third electrode is disposed on the substrate and used as a working electrode. The chemical reagent layer at least covers a sensing section of the third electrode so as to permit the third electrode to selectively cooperate with the first electrode or the first and second electrodes to measure a physiological signal in response to the physiological parameter of the analyte.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Inventors: Chun-Mu Huang, Chieh-Hsing Chen, Heng-Chia Chang, Chi-Hao Chen, Chien-Chung Chen
  • Publication number: 20240152735
    Abstract: Provided is a system for detecting an anomaly in a multivariate time series that includes at least one processor programmed or configured to receive a dataset of a plurality of data instances, wherein each data instance comprises a time series of data points, determine a set of target data instances based on the dataset, determine a set of historical data instances based on the dataset, generate, based on the set of target data instances, a true value matrix, a true frequency matrix, and a true correlation matrix, generate a forecast value matrix, a forecast frequency matrix, and a forecast correlation matrix based on the set of target data instances and the set of historical data instances, determine an amount of forecasting error, and determine whether the amount of forecasting error corresponds to an anomalous event associated with the dataset of data instances. Methods and computer program products are also provided.
    Type: Application
    Filed: June 10, 2022
    Publication date: May 9, 2024
    Applicant: Visa International Service Association
    Inventors: Lan Wang, Yu-San Lin, Yuhang Wu, Huiyuan Chen, Fei Wang, Hao Yang
  • Publication number: 20240154452
    Abstract: A charging circuitry includes a power electronic converter, a current sensor, a voltage boost/buck controller and a charging mode controller. The power electronic converter is configured to charge or discharge a supercapacitor according to a control command. The current sensor is coupled to the supercapacitor for detecting a first sensed voltage and a second sensed voltage. The voltage boost/buck controller is configured to generate the control command and a current command according to the first and second sensed voltages and an overall feedback. The charging mode controller is configured to generate a current feedback and a voltage feedback to the voltage boost/buck controller according to a driving voltage, the current command and a third sensed voltage of the supercapacitor. The third sensed voltage, the current feedback and the voltage feedback are superposed as the overall feedback and then inputted to the same input terminal of the voltage boost/buck converter.
    Type: Application
    Filed: March 8, 2023
    Publication date: May 9, 2024
    Inventors: Si-Wei CHEN, Wen-Hao KUO
  • Publication number: 20240151609
    Abstract: A method of selecting a group of multimode optical fibers, includes comparing a first effective modal bandwidth at a first wavelength of a multimode optical fiber with a first effective modal bandwidth threshold at the first wavelength, the multimode optical fiber being in a group of multimode optical fibers meeting a first OM standard, wherein the first wavelength is from 844 nm to 863 nm; and categorizing the multimode optical fiber as passing a transmission distance requirement if the first effective modal bandwidth of the first multimode optical fiber is greater than or equal to the first effective modal bandwidth threshold; wherein the transmission distance is defined in a transceiver specification, wherein the transceiver specification is one or more of: (a) an 800G bidirectional (BiDi) transceiver specification, or (b) a 100G/lane based MM VCSEL transceiver specification, or (c) a 25Gbaud based transceiver specification, or (d) 50G PAM4 based transceiver specification.
    Type: Application
    Filed: October 20, 2023
    Publication date: May 9, 2024
    Inventors: Zoren Dene Bullock, Xin Chen, Hao Dong, Ming-Jun Li, Simit Mayank Patel
  • Publication number: 20240154010
    Abstract: Embodiments of the present disclosure relates to a semiconductor device structure. The structure includes a source/drain epitaxial feature disposed over a substrate, a first interlayer dielectric (ILD) disposed over the source/drain epitaxial feature, a second ILD disposed over the first ILD. The second ILD includes a first dopant species having an atomic radius equal to or greater than silicon and a second dopant species having an atomic mass less than 15. The structure also includes a first conductive feature disposed in the second ILD, and a second conductive feature disposed over the source/drain epitaxial feature, the second conductive feature extending through the first ILD and in contact with the first conductive feature.
    Type: Application
    Filed: January 22, 2023
    Publication date: May 9, 2024
    Inventors: Meng-Han Chou, Kuo-Ju Chen, Su-Hao Liu, Huicheng Chang, Yee-Chia Yeo
  • Publication number: 20240153958
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.
    Type: Application
    Filed: January 7, 2024
    Publication date: May 9, 2024
    Inventors: Jung-Hung CHANG, Zhi-Chang LIN, Shih-Cheng CHEN, Chien Ning YAO, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20240154019
    Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor having a first gate dielectric layer, a second transistor having a second gate dielectric layer, and a third transistor having a third gate dielectric layer. The first gate dielectric layer includes a first concentration of a dipole layer material, the second gate dielectric layer includes a second concentration of the dipole layer material, and the third gate dielectric layer includes a third concentration of the dipole layer material. The dipole layer material includes lanthanum oxide, aluminum oxide, or yittrium oxide. The first concentration is greater than the second concentration and the second concentration is greater than the third concentration.
    Type: Application
    Filed: December 29, 2023
    Publication date: May 9, 2024
    Inventors: Chia-Hao Pao, Chih-Hsuan Chen, Yu-Kuan Lin
  • Publication number: 20240154043
    Abstract: A semiconductor device includes channel members vertically stacked, a gate structure wrapping around the channel members, a gate spacer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, and an inner spacer layer interposing the gate structure and the epitaxial feature. In a top view of the semiconductor device, the inner spacer layer has side portions in physical contact with the gate spacer and a middle portion stacked between the side portions. In a lengthwise direction of the channel members, the middle portion of the inner spacer layer is thicker than the side portions of the inner spacer layer.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 9, 2024
    Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240154071
    Abstract: Provided is a light-emitting panel comprising a substrate, a plurality of light-emitting device, and a reflection sheet, wherein the plurality of light-emitting devices and the reflection sheet are disposed on the same side of the substrate, the reflection sheet comprises a plurality of first through-holes, which are in one-to-one correspondence with the plurality of light-emitting devices, and the reflection sheet at an edge of the plurality of first through-holes is configured to wrap around an edge of the plurality of light-emitting device, and a gap between an edge of the plurality of first through-holes and an edge adjacent to the plurality of light-emitting devices is less than 0.1 mm, so that a distance between the edge of the plurality of first through holes and the edge of the plurality of light-emitting devices is reduced, and the size and width of the windowed area are reduced.
    Type: Application
    Filed: December 19, 2022
    Publication date: May 9, 2024
    Applicant: TCL China Star Optoelectronics Technology Co., Ltd.
    Inventors: Hongzhao DENG, Jing LIU, Hao CHEN, Linnan CHEN
  • Publication number: 20240154426
    Abstract: Disclosed is a method and system for grid connection management of renewable energy generation, the method comprises: obtaining operating condition data of a first power supply, a second power supply, a power grid, and a load in a preset period; establishing a first optimal control model according to the first condition data, and establishing a second optimal control model; monitoring grid connection management status of the first optimal control model and the second optimal control model; analyzing stability when the first optimal control model is switched to the second optimal control model. The beneficial effects of this disclosure are: completing the switch from the first optimal control model to the second optimal control model in the renewable energy generation grid connection management, which improves the smoothness of control model switching under different load conditions in the renewable energy generation process.
    Type: Application
    Filed: December 6, 2022
    Publication date: May 9, 2024
    Inventors: YINGJIE CHEN, GE PENG, HAO BIAN, JUN ZHANG, LEI TIAN, LINCHUAN LI
  • Patent number: 11974842
    Abstract: An implantable micro-biosensor a substrate, a first electrode, a second electrode, a third electrode, and a chemical reagent layer. The first electrode is disposed on the substrate and used as a counter electrode. The second electrode is disposed on the substrate and spaced apart from the first electrode. The third electrode is disposed on the substrate and used as a working electrode. The chemical reagent layer at least covers a sensing section of the third electrode so as to permit the third electrode to selectively cooperate with the first electrode or the first and second electrodes to measure a physiological signal in response to the physiological parameter of the analyte.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: May 7, 2024
    Assignee: Bionime Corporation
    Inventors: Chun-Mu Huang, Chieh-Hsing Chen, Heng-Chia Chang, Chi-Hao Chen, Chien-Chung Chen
  • Patent number: D1026897
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: May 14, 2024
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Ming-Chen Chen, Tong-Shen Hsiung, Chia-Hao Hung