Patents by Inventor Hao Liu

Hao Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240084393
    Abstract: A molecular marker for identifying DNA methylation and thereby detecting the benignity or malignancy of a lung nodule is disclosed. The molecular marker for identifying DNA methylation includes the sequence of, or the completely complementary sequence to, SEQ ID NO:6 or a continuous fragment of at least 55% of the full length of the sequence of, or the completely complementary sequence to, SEQ ID NO:6. Also disclosed are applications of the molecular marker for identifying DNA methylation, including a corresponding detection reagent kit and a corresponding detection method. The disclosed molecular marker combinations for identifying DNA methylation are highly correlated to lung cancer, are highly sensitive and specific when used to detect the benignity or malignancy of a lung nodule, and can increase the detection rate of malignant lung nodules while lowering the false positive rate.
    Type: Application
    Filed: June 17, 2023
    Publication date: March 14, 2024
    Inventors: Zhujia YE, Hao YANG, Yanying LIU, Jinsheng TAO, Xi LUO, Jiehan XU, Zhiwei CHEN, Jianbing FAN
  • Publication number: 20240084445
    Abstract: A leak check is performed on a semiconductor wafer processing tool that includes a process chamber and process gas lines, and a semiconductor wafer is processed using the semiconductor wafer processing tool if the leak check passes. Each gas line includes a mass flow controller (MFC) and normally closed valves including an upstream and downstream valves upstream and downstream of the MFC. Leak checking includes: leak checking up to the downstream valves of the gas lines with the upstream valves closed and the downstream valves of the gas lines closed; and leak checking up to the upstream valve of each the process gas line with the upstream valves of the of the process gas lines closed and with the downstream valve of the of the process gas line being leak checked open and the downstream valve of every other process gas line closed.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 14, 2024
    Inventors: Chih-Wei Chou, Yuan-Hsin Chi, Chih-Hao Yang, Hung-Chih Wang, Yu-Chi Liu, Sheng-Yuan Lin
  • Publication number: 20240088392
    Abstract: Provided is an electrode mixture including: an electrode active material; an organic solvent; a binder; and an additive; wherein the binder contains a fluorine-containing copolymer containing a vinylidene fluoride unit and a fluorinated monomer unit, provided that the vinylidene fluoride unit is excluded from the fluorinated monomer unit; the additive is a polymer material containing the following repeating unit: —[CH2—CHR]— wherein R is a chain or cyclic amide group, a nitrile group, or a substituted alkyl group formed by substituting at least one of hydrogen atoms of an alkyl group having 1 to 4 carbon atoms with a chain or cyclic amide group or a nitrile group; a content of the binder is 0.1 to 1.6 parts by mass with respect to 100 parts by mass of the electrode active material; and a content of the additive is 0.001 to 0.2 parts by mass with respect to 100 parts by mass of the electrode active material.
    Type: Application
    Filed: March 3, 2023
    Publication date: March 14, 2024
    Applicants: DAIKIN INDUSTRIES, LTD., DAIKIN FLUOROCHEMICALS (CHINA) CO., LTD.
    Inventors: Kanako ARAI, Ryouichi YANO, Yuki YOTSUMOTO, Pei Qi LIU, En Hao ZHANG
  • Publication number: 20240086362
    Abstract: A key-value store and a file system are integrated together to provide improved operations. The key-value store can include a log engine, a hash engine, a sorting engine, and a garbage collection manager. The features of the key-value store can be configured to reduce the number of I/O operations involving the file system, thereby improving read efficiency, reducing write latency, and reducing write amplification issues inherent in the combined key-value store and file system.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 14, 2024
    Inventors: Hao Wang, Jiaxin Ou, Sheng Qiu, Yi Wang, Zhengyu Yang, Yizheng Jiao, Jingwei Zhang, Jianyang Hu, Yang Liu, Ming Zhao, Hui Zhang, Kuankuan Guo, Huan Sun, Yinlin Zhang
  • Publication number: 20240086717
    Abstract: Disclosed is a model training control method based on asynchronous federated learning, an electronic device and a storage medium, relating to data processing technical field, and especially to technical fields such as edge computing and machine learning. The method includes: sending a first parameter of a first global model to a plurality of edge devices; receiving a second parameter of a second global model returned by a first edge device of plurality of edge devices, the second global model being a global model obtained after the first edge device trains the first global model according to a local data set; and sending a third parameter of a third global model to a second edge device of the plurality of edge devices in a case of the third global model is obtained based on aggregation of at least one second global model.
    Type: Application
    Filed: January 18, 2023
    Publication date: March 14, 2024
    Inventors: Ji LIU, Hao TIAN, Ruipu ZHOU, Dejing DOU
  • Publication number: 20240088225
    Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
  • Publication number: 20240087945
    Abstract: Semiconductor processing apparatuses and methods are provided in which an electrostatic discharge (ESD) prevention layer is utilized to prevent or reduce ESD events from occurring between a semiconductor wafer and one or more components of the apparatuses. In some embodiments, a semiconductor processing apparatus includes a wafer handling structure that is configured to support a semiconductor wafer during processing of the semiconductor wafer. The apparatus further includes an ESD prevention layer on the wafer handling structure. The ESD prevention layer includes a first material and a second material, and the second material has an electrical conductivity that is greater than an electrical conductivity of the first material.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Tsai-Hao HUNG, Ping-Cheng KO, Tzu-Yang LIN, Fang-Yu LIU, Cheng-Han WU
  • Publication number: 20240086625
    Abstract: An information processing method and apparatus, a terminal, and a storage medium. The information processing method comprises: determining first content in response to a first operation event of a first control in a first document (S11); and adding the first content to the first document on the basis of content information and type information of the first content (S12). The type information comprises first type information and/or second type information, the second type information having an association with the first type information. In the described method, first content can be added to a first document according to content information and type information of the first content, so as to distinguish different ways of adding the first content.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Lu ZHANG, Wenzong MA, Xinlei GUO, Xiaolin FANG, Hao HUANG, Liang CHEN, Lanjin ZHOU, Linghui ZHOU, Yingtao LIU, Dirun HUANG, Xuebing ZENG, Zejian LIN, Yingjie YOU, Yunzhao TONG, Yuxiang CHEN, Jiawei CHEN
  • Publication number: 20240088980
    Abstract: Certain aspects of the present disclosure relate to wireless communications, and more particularly, to techniques for beam determination, multi-user transmission, and channel state variance information (CSVI) reporting in a holographic multiple input multiple output (MIMO) system.
    Type: Application
    Filed: March 26, 2021
    Publication date: March 14, 2024
    Inventors: Min HUANG, Wei XI, Chao WEI, Yu ZHANG, Hao XU, Chenxi HAO, Rui HU, Liangming WU, Kangqi LIU, Qiaoyu LI, Jing DAI, Changlong XU
  • Patent number: 11927851
    Abstract: A display panel and a display device are provided. The display panel includes a first base substrate; a second base substrate opposite to the first base substrate; a liquid crystal layer between the first and second base substrates; a first alignment film at a side of the first base substrate facing the liquid crystal layer; a second alignment film at a side of the second base substrate facing the liquid crystal layer; a polarizer at a side of the first base substrate away from the liquid crystal layer; and a quarter-wave plate between the polarizer and the first base substrate. An angle between a center line of an included angle between the first alignment direction of the first alignment film and the second alignment direction of the second alignment film and a slow axis of the quarter-wave plate is in a range from 75 to 105 degrees.
    Type: Grant
    Filed: January 18, 2021
    Date of Patent: March 12, 2024
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hao Liu, Ruichen Zhang, Kaixuan Wang, Yanqing Chen, Zhao Zhang, Yanni Liu, Li Tian
  • Patent number: 11930530
    Abstract: Certain aspects of the present disclosure provide a method for wireless communications by a transmitter UE. The method generally includes receiving, from a network entity, a downlink control information (DCI) allocating resources in an unlicensed frequency band for multiple physical sidelink shared channel (PSSCH) transmissions to at least one receiver UE across transmission time intervals (TTIs), performing a listen-before-talk (LBT) channel access procedure in the TTIs, and transmitting at least one LBT report to the network entity on a physical uplink control channel (PUCCH) resource that occurs before another PUCCH resource used for transmitting acknowledgment feedback for the PSSCH transmissions.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: March 12, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Chih-Hao Liu, Jing Sun, Yisheng Xue, Xiaoxia Zhang, Piyush Gupta, Sony Akkarakaran, Tao Luo, Juan Montojo, Peter Gaal
  • Patent number: 11930533
    Abstract: Channel occupancy time (COT) aware sensing and resource selection for new radio-unlicensed (NR-U) sidelink operations is disclosed. A first sidelink user equipment (UE) determines a sensing window or resource selection window (RSW) based on a projected listen-before-talk (LBT) completion time. The UE may sense for a subset of sideline resources within the RSW and COT-SI from a neighboring sidelink UE including identification of a COT initiated by the neighboring UE and one or more parameters associated with the COT. The UE may identify in-COT resources of located within the COT and out-of-COT resources located outside of the COT and then randomly select a set of transmission resources from the in-COT and out-of-COT resources. The UE may then transmit to a second UE using the set of transmission resources.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: March 12, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Chih-Hao Liu, Yisheng Xue, Jing Sun, Xiaoxia Zhang, Ozcan Ozturk, Tao Luo, Juan Montojo, Peter Gaal
  • Patent number: 11930498
    Abstract: Some aspects described herein relate transmitting, to a receiving UE, a sidelink control information (SCI) that schedules multiple transport blocks (TBs) of shared channel communications in multiple time divisions, and transmitting, to the receiving UE and based on the SCI, the multiple TBs of shared channel communications in the multiple time divisions. Other aspects relate to receiving, from a transmitting UE, a SCI that schedules multiple TBs of shared channel communications in multiple time divisions, and receiving, from the transmitting UE and based on the SCI, the multiple TBs of shared channel communications in the multiple time divisions. Additional aspects relate to configuring the UEs in this regard.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: March 12, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Chih-Hao Liu, Yisheng Xue, Jing Sun, Xiaoxia Zhang
  • Patent number: 11925440
    Abstract: A single smart health device able to monitor all physiological aspects of a human body includes a body fluid detection module, a temperature detection module, an electrocardiogram detection module, and a control module. The body fluid detection module tests and detects amounts of biological substances in body fluids. The temperature detection module detects a temperature of the human body. The electrocardiogram detection module detects a heart rate of the human body. The control module is electrically connected to the body fluid detection module, the temperature detection module, and the electrocardiogram detection module, and obtains the detected amounts of biological substances, the detected temperature, and the detected heart rate.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: March 12, 2024
    Assignee: Jiangyu Kangjian Innovation Medical Technology(Chengdu) Co., Ltd
    Inventors: Yu-Chao Li, Lien-Yu Lin, Ying-Wei Sheng, Chieh Kuo, Ping-Hao Liu
  • Publication number: 20240081077
    Abstract: A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Applicants: Taiwan Semiconductor Manufacturing Company, Ltd., National Yang Ming Chiao Tung University
    Inventors: Po-Tsun Liu, Meng-Han Lin, Zhen-Hao Li, Tsung-Che Chiang, Bo-Feng Young, Hsin-Yi Huang, Sai-Hooi Yeong, Yu-Ming Lin
  • Publication number: 20240081103
    Abstract: A display substrate and a display device are disclosed. In the display substrate, a plurality of openings include a plurality of opening groups, the plurality of opening groups include a plurality of opening group rows, each of the opening groups includes a first opening and a second opening, the plurality of opening group rows includes a first opening group row and a second opening group row, the spacer is located between the first opening of the first opening group row and the second opening of the second opening group row, an orthographic projection of the first opening includes a first long edge, and an orthographic projection of the second opening includes a second long edge, the first long edge is parallel to the second long edge, an extension line of the first long edge is misaligned from an extension line of the second long edge.
    Type: Application
    Filed: October 11, 2023
    Publication date: March 7, 2024
    Inventors: Hao ZHANG, Tingliang LIU, Yu WANG, Huijun LI, Huijuan YANG, Xiaofeng JIANG, Xin ZHANG, Jie DAI, Lu BAI, Pengfei YU, Tinghua SHANG
  • Publication number: 20240080180
    Abstract: The federated learning system includes a moderator and client devices. Each client device performs a method for verifying model update as follows: receiving a hash function and a general model; training a client model according to the general model and raw data; calculating a difference as an update parameter between the general model and the client model, sending the update parameter to the moderator; inputting the update parameter to the hash function to generate a hash value; sending the hash value to other client devices, and receiving other hash values; summing all the hash values to generate a trust value; receiving an aggregation parameter calculated according to the update parameters; inputting the aggregation parameter to the hash function to generate a to-be-verified value; and updating the client model according to the aggregation parameter when the to-be-verified value equals the trust value.
    Type: Application
    Filed: December 20, 2022
    Publication date: March 7, 2024
    Inventors: Chih-Fan HSU, Wei-Chao CHEN, Jing-Lun Huang, Ming-Ching Chang, Feng-Hao Liu
  • Publication number: 20240079451
    Abstract: A semiconductor device includes a substrate, first and second stacks of semiconductor nanosheets, a gate structure, first and second strained layers and first and second dielectric walls. The substrate includes first and second fins. The first and second stacks of semiconductor nanosheets are disposed on the first and second fins respectively. The gate structure wraps the first and second stacks of semiconductor nanosheets. The first and second strained layers are respectively disposed on the first and second fins and abutting the first and second stacks of semiconductor nanosheets. The first dielectric wall is disposed on the substrate and located between the first and second strained layers. The second dielectric wall is disposed on the first dielectric wall and located between the first and second strained layers. A top surface of the second dielectric wall is lower than top surfaces of the first and second strained layers.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun Lin, Tzu-Hung Liu, Chun-Jun LIN, Chih-Hao Chang, Jhon Jhy Liaw
  • Publication number: 20240077760
    Abstract: A display device includes: a frame, including a frame body, a first protrusion disposed on the frame body, and a second protrusion disposed on the frame body, the second protrusion including at least one stepped portion; a display panel, located on a side of one stepped portion of the at least one stepped portion close to a light emitting surface of the display device and located on an inner side of the frame body; and a planar back housing, fixed on the inner side of the frame body and a side of the first protrusion away from the light emitting surface.
    Type: Application
    Filed: October 31, 2023
    Publication date: March 7, 2024
    Inventors: Hao LIU, Yunben SHEN, Guangning HAO, Tao NI, Yang LIU, Lihua SHENG
  • Patent number: 11923392
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Jen-Cheng Liu, Kazuaki Hashimoto, Ming-En Chen, Shyh-Fann Ting, Shuang-Ji Tsai, Wei-Chieh Chiang