Patents by Inventor Hao Nguyen
Hao Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Stereographic image detail uniformity of a panoramic video capture device having an optical gradient
Patent number: 9860444Abstract: A stereographic image associated with a panoramic camera can be identified. The panoramic camera can include of a set of lenses and an image sensor. A pixel degradation curve associated with the image and/or the hardware of the panoramic camera can be determined, as can a sensor geometry of an image sensor used by the panoramic camera. A fixed smoothing function based on the pixel degradation curve and/or the sensor geometry can be created. The fixed smoothing function can be applied to a stereographic image to modify the image so it includes substantially uniform image detail per image region.Type: GrantFiled: December 22, 2014Date of Patent: January 2, 2018Assignee: HOYOS INTEGRITY CORPORATIONInventors: Moises De La Cruz, John Shemelynce, Hao Nguyen, Biren Patel, Gustavo D. Leizerovich, Amit Verma -
Publication number: 20170256317Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.Type: ApplicationFiled: May 19, 2017Publication date: September 7, 2017Applicant: SanDisk Technologies LLCInventors: Hao Nguyen, Man Mui, Khanh Nguyen, Seungpil Lee, Toru Ishigaki, Yingda Dong
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Publication number: 20170169867Abstract: The present disclosure describes a system, a circuit, and method for process and temperature compensation in an integrated circuit. For example, the system includes a bus, a data latch, and a voltage generator. The data latch includes a plurality of transistors coupled to the bus. The voltage generator includes a tracking transistor with one or more physical characteristics that substantially match one or more respective physical characteristics—e.g., gate width and gate length dimensions—of at least one of the plurality of transistors in the data latch. The voltage generator is configured to adjust a pre-charged voltage on the bus based on an electrical characteristic of the tracking transistor.Type: ApplicationFiled: May 11, 2016Publication date: June 15, 2017Applicant: SanDisk Technologies, LLCInventors: Amul DESAI, Hao Nguyen, Man Mui, Ohwon Kwon
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Patent number: 9659656Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.Type: GrantFiled: March 7, 2016Date of Patent: May 23, 2017Assignee: SanDisk Technologies LLCInventors: Hao Nguyen, Man Mui, Khanh Nguyen, Seungpil Lee, Toru Ishigaki, Yingda Dong
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Patent number: 9633742Abstract: In non-volatile memory circuits, the amount of time needed for bit lines to settle can vary significantly depending on the location of the blocks selected. For example, in a sensing operation, the amount of time for bit lines to settle when being pre-charged by sense amplifiers will be shorter for blocks near the sense amps than for far side blocks. These variations can be particularly acute in high density memory structures, such as in 3D NAND memory, such as that of the BiCS variety. Rather than use the same timing for all blocks, the blocks can be segmented into groups based on their proximity to the sense amps. When performing a sensing operation, the timing can be adjusted based on the block group to which a selected page of memory cells belongs.Type: GrantFiled: July 10, 2014Date of Patent: April 25, 2017Assignee: SanDisk Technologies LLCInventors: Amul Dhirajbhai Desai, Hao Nguyen, Seungpil Lee, Man Mui
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Patent number: 9595338Abstract: In NAND Flash memory, bit line precharge/discharge times can be a main component in determining program, erase and read performance. In a conventional arrangement bit line levels are set by the sense amps and bit lines are discharged to a source line level is through the sense amplifier path. Under this arrangement, precharge/discharge times are dominated by the far-side (relative to the sense amps) based on the bit lines' RC constant. Reduction of bit line precharge/discharge times, therefore, improves NAND Flash performance and subsequently the overall system performance. To addresses this, an additional path is introduced between bit lines to the common source level through the use of dummy NAND strings. In an exemplary 3D-NAND (BiCS) based embodiment, the dummy NAND strings are taken from dummy blocks, where the dummy blocks can be placed throughout the array to evenly distribute the discharging current.Type: GrantFiled: September 24, 2014Date of Patent: March 14, 2017Assignee: SanDisk Technologies LLCInventors: Juan Carlos Lee, Hao Nguyen, Man Mui, Tien-chien Kuo, Yuki Mizutani
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Patent number: 9542816Abstract: A wearable alert device includes an audio transducer and driver circuit that allows selection of either a high or low volume setting for driving the transducer. The driver circuit is operable in a single ended mode for low volume and a double ended mode for high volume. The single ended mode holds one terminal of the transducer low while the other is driven in correspondence with a clock signal, while the double ended mode drives one terminal in correspondence with the clock signal and the other terminal is inverted from the clock signal. The transducer is activated in response to an alert event, and can be driven according to a profile or pattern.Type: GrantFiled: May 15, 2014Date of Patent: January 10, 2017Assignee: VSN TECHNOLOGIES, INC.Inventors: Tal Mor, Amit Verma, Vinosh Diptee, Moises De La Cruz, Hao Nguyen
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Publication number: 20160327299Abstract: A thermostat includes a housing having a base, a display mount cantilevered from the base, and a case defining an interior volume extending between a front surface and a rear surface, a touch-sensitive display configured to display visual media and receive user inputs, wherein the touch-sensitive display is attached to the display mount, processing electronics on a circuit board positioned at least partially within the interior volume of the case, wherein the processing electronics are configured to operate the touch-sensitive display, and a mounting bracket configured to attach to a mounting location, wherein the mounting bracket includes a frame defining an aperture and the case extends through the aperture so that the frame is located between the front and rear surfaces of the case.Type: ApplicationFiled: May 4, 2016Publication date: November 10, 2016Applicant: Johnson Controls Technology CompanyInventors: Joseph R. Ribbich, John Peter Cipolla, Sudhi Sinha, Michael L. Ribbich, Amit Verma, Vinosh C. Diptee, Hao A. Nguyen, Julio A. Abdala, Juan Guillermo Alvarez, Felippe M. Bicudo, Patricia Ellis Douglass, Claudio Santiago Ribeiro
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Patent number: 9444945Abstract: A system of an alert puck, a mobile communication device, and an alert server for facilitating a VOIP session with the mobile communication device responsive to an emergency event triggered by the alert puck. The alert puck comprises a housing enclosing a sealed volume, a power supply and control circuitry that includes a personal area network (PAN) interface. The mobile communication device comprises an operating system, an alert application executing upon the operating system, and a wireless transceiver. The alert server contacts a set of one or more previously defined contact devices, conveys an emergency message, and facilitates the VOIP session with the alert application, when a button is pressed on the alert puck.Type: GrantFiled: May 30, 2014Date of Patent: September 13, 2016Assignee: VSN TECHNOLOGIES, INC.Inventors: Amit Verma, Julio A. Abdala, Moises De La Cruz, Hao Nguyen, Guillermo Padin, Biren Patel, Jose Ruiz, Vinosh Diptee
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Publication number: 20160189778Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.Type: ApplicationFiled: March 7, 2016Publication date: June 30, 2016Applicant: SanDisk Technologies, Inc.Inventors: Hao NGUYEN, Man MUI, Khanh NGUYEN, Seungpil LEE, Toru ISHIGAKI, Yingda DONG
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Patent number: 9349468Abstract: Rather than supply an internal node of a non-volatile memory's sense amplifier from a supply level through a transistor by applying a voltage to the transistor's gate to clamp the node, the internal node is supplied by an op-amp through a pass gate. The op-amp receives feedback from above the pass gate. This allows a desired voltage level to be more quickly and accurately established on the node. Using a two-step reference level for the op-amp can further increases speed and accuracy. Biasing the op-amp with the external power supply can offer additional advantages.Type: GrantFiled: August 25, 2014Date of Patent: May 24, 2016Assignee: SanDisk Technologies, Inc.Inventors: Kenneth Louie, Khanh Nguyen, Hao Nguyen
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Patent number: 9305648Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.Type: GrantFiled: August 20, 2014Date of Patent: April 5, 2016Assignee: SanDisk Technologies, Inc.Inventors: Hao Nguyen, Man Mui, Khanh Nguyen, Seungpil Lee, Toru Ishigaki, Yingda Dong
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Publication number: 20160086671Abstract: In NAND Flash memory, bit line precharge/discharge times can be a main component in determining program, erase and read performance. In a conventional arrangement bit line levels are set by the sense amps and bit lines are discharged to a source line level is through the sense amplifier path. Under this arrangement, precharge/discharge times are dominated by the far-side (relative to the sense amps) based on the bit lines' RC constant. Reduction of bit line precharge/discharge times, therefore, improves NAND Flash performance and subsequently the overall system performance. To addresses this, an additional path is introduced between bit lines to the common source level through the use of dummy NAND strings. In an exemplary 3D-NAND (BiCS) based embodiment, the dummy NAND strings are taken from dummy blocks, where the dummy blocks can be placed throughout the array to evenly distribute the discharging current.Type: ApplicationFiled: September 24, 2014Publication date: March 24, 2016Inventors: Juan Carlos Lee, Hao Nguyen, Man Mui, Tien-chien Kuo, Yuki Mizutani
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Publication number: 20160055916Abstract: Rather than supply an internal node of a non-volatile memory's sense amplifier from a supply level through a transistor by applying a voltage to the transistor's gate to clamp the node, the internal node is supplied by an op-amp through a pass gate. The op-amp receives feedback from above the pass gate. This allows a desired voltage level to be more quickly and accurately established on the node. Using a two-step reference level for the op-amp can further increases speed and accuracy. Biasing the op-amp with the external power supply can offer additional advantages.Type: ApplicationFiled: August 25, 2014Publication date: February 25, 2016Inventors: Kenneth Louie, Khanh Nguyen, Hao Nguyen
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Publication number: 20160055911Abstract: In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage.Type: ApplicationFiled: August 20, 2014Publication date: February 25, 2016Inventors: Hao Nguyen, Man Mui, Khanh Nguyen, Seungpil Lee, Toru Ishigaki, Yingda Dong
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Publication number: 20160012903Abstract: In non-volatile memory circuits, the amount of time needed for bit lines to settle can vary significantly depending on the location of the blocks selected. For example, in a sensing operation, the amount of time for bit lines to settle when being pre-charged by sense amplifiers will be shorter for blocks near the sense amps than for far side blocks. These variations can be particularly acute in high density memory structures, such as in 3D NAND memory, such as that of the BiCS variety. Rather than use the same timing for all blocks, the blocks can be segmented into groups based on their proximity to the sense amps. When performing a sensing operation, the timing can be adjusted based on the block group to which a selected page of memory cells belongs.Type: ApplicationFiled: July 10, 2014Publication date: January 14, 2016Inventors: Amul Dhirajbhai Desai, Hao Nguyen, Seungpil Lee, Man Mui
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Patent number: 8824989Abstract: Implementations are directed to predicting signal degradation at receivers used to display a programming service. The receivers capture signal strength data that is then transmitted to a processing location, which may be associated with a provider of the programming service. A signal degradation detector at the provider operates to predict whether or not a future unacceptable signal quality will occur within a time interval. The prediction may be based on a test quantity calculated from signals captured at the receiver and based on a figure of merit for the geographic locale in which the receiver is located. A maintenance call may be initiated for those receivers that have such a poor signal quality.Type: GrantFiled: December 21, 2012Date of Patent: September 2, 2014Assignee: EchoStar Technologies L.L.C.Inventors: Robert J.V. Jackson, Tianhua Zhang, Moutaz Elkaissi, Hao Nguyen, Jorge Sotelo, Wendell Blackman, Greg Goldey
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Patent number: 8755234Abstract: A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.Type: GrantFiled: October 7, 2013Date of Patent: June 17, 2014Assignee: SanDisk Technologies Inc.Inventors: Ken Oowada, Yingda Dong, Gerrit Jan Hemink, Man Lung Mui, Hao Nguyen, Seungpil Lee, Jong Park, Fanglin Zhang
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Publication number: 20140036601Abstract: A non-volatile storage system that performs programming and reading processes. The programming process includes coarse/fine programming and verify operations. Programming is verified by testing for two different threshold voltage levels while applying the same voltage level to the control gate of a memory cell by testing for current levels through the memory cells and adjusting the current levels tested for based on current temperature such that the difference between the two effective tested threshold voltage levels remains constant over temperature variation.Type: ApplicationFiled: October 7, 2013Publication date: February 6, 2014Applicant: SANDISK TECHNOLOGIES INC.Inventors: Ken Oowada, Yingda Dong, Gerrit Jan Hemink, Man Lung Mui, Hao Nguyen, Seungpil Lee, Jong Park, Fanglin Zhang
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Patent number: D790369Type: GrantFiled: December 11, 2015Date of Patent: June 27, 2017Assignee: Johnson Controls Technology CompanyInventors: Sudhi Sinha, Joseph R. Ribbich, Michael L. Ribbich, Charles J. Gaidish, John Peter Cipolla, Amit Verma, Vinosh C. Diptee, Hao A. Nguyen, Julio A. Abdala, Juan Guillermo Alvarez, Felippe M. Bicudo, Patricia Ellis Douglass, Claudio Santiago Ribeiro