Patents by Inventor Hao Pan
Hao Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990381Abstract: In an embodiment, a device includes: a package component including: integrated circuit dies; an encapsulant around the integrated circuit dies; a redistribution structure over the encapsulant and the integrated circuit dies, the redistribution structure being electrically coupled to the integrated circuit dies; sockets over the redistribution structure, the sockets being electrically coupled to the redistribution structure; and a support ring over the redistribution structure and surrounding the sockets, the support ring being disposed along outermost edges of the redistribution structure, the support ring at least partially laterally overlapping the redistribution structure.Type: GrantFiled: November 14, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Rong Chun, Kuo Lung Pan, Tin-Hao Kuo, Hao-Yi Tsai, Pei-Hsuan Lee, Chien Ling Hwang, Yu-Chia Lai, Po-Yuan Teng, Chen-Hua Yu
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Patent number: 11990471Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.Type: GrantFiled: August 10, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Cheng Chiang, Shi Ning Ju, Guan-Lin Chen, Kuan-Ting Pan, Chih-Hao Wang
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Patent number: 11990374Abstract: Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers.Type: GrantFiled: December 19, 2022Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuan-Ting Pan, Kuo-Cheng Chiang, Shi Ning Ju, Yi-Ruei Jhan, Kuan-Lun Cheng, Chih-Hao Wang
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Publication number: 20240161512Abstract: In one embodiment, a system generates an image using either a first or a second image signal processing (ISP) algorithm, where the first or second ISP algorithm is applied to raw image data of a camera of an autonomous driving vehicle (ADV) to generate the image. The system applies a machine learning model to the image to identify a representation of an obstacle, where the machine learning model is generated by a few shots learning algorithm that contrasts labeled data of a positive training sample from images corresponding to the first and second ISP algorithms to labeled data of a negative training sample from images corresponding to the first and second ISP algorithm. The system determines a classification and a location of the obstacle based on the representation of the obstacle. The system plans a motion control of the ADV based on the classification and location of the detected object.Type: ApplicationFiled: November 16, 2022Publication date: May 16, 2024Inventors: SHU JIANG, SZU-HAO WU, JEONG HO LYU, LINPENG CHENG, HAO LIU, HELEN K. PAN
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Publication number: 20240163820Abstract: Presented are systems, methods, apparatuses, or computer-readable media for configuring reference signaling. A wireless communication device may determine a set of resources. A number of resources in the set may be equal to or more than one and the set satisfies a character. Each of the resources may be associated with a respective value of information.Type: ApplicationFiled: November 27, 2023Publication date: May 16, 2024Applicant: ZTE CORPORATIONInventors: Shujuan ZHANG, Hao WU, Yang ZHANG, Chuangxin JIANG, Yu PAN, Zhaohua LU
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Publication number: 20240158952Abstract: An apparatus for regulating at least one hot zone for growing a silicon single crystal which is arranged inside a crystal puller includes an insulator, a first control unit and a second control unit. The insulator has a top on which a reflector is fixedly arranged. The first control unit is configured to keep a position of a crucible in a height direction unchanged during growth of the silicon single crystal. The second control unit is configured to move the insulator along a vertical direction during growth of the silicon single crystal, so as to keep a distance between a bottom of the reflector and a liquid surface of silicon melt constant.Type: ApplicationFiled: September 29, 2022Publication date: May 16, 2024Inventors: Hao PAN, Hyunguk JEON
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Patent number: 11981666Abstract: Provided are a GLP-1 receptor agonist compound and a composition and use thereof. The compound can be used for treating or preventing GLP-1 receptor-mediated diseases or disorders and related diseases or disorders.Type: GrantFiled: September 13, 2023Date of Patent: May 14, 2024Assignee: HANGZHOU ZHONGMEIHUADONG PHARMACEUTICAL CO., LTD.Inventors: Wenqiang Zhai, Zhimin Zhang, Zhe Wang, Hao Pan, Liubin Guo, Qian Wang
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Publication number: 20240154014Abstract: The present disclosure provides a forksheet structure in a semiconductor device and methods of manufacturing thereof. The forksheet structure according to the present disclosure includes a dielectric wall disposed between two channel regions inside a gate structure and without extending through the sidewall spacers to the source/drain regions. In some embodiments, a cut metal gate (CMG) dielectric structure is formed in the gate structure along with the dielectric walls. A gate dielectric layer is in contact with the dielectric wall. In some embodiments, the dielectric layer surrounds semiconductor channels in the channel region. In other embodiments, the gate dielectric layer surrounds a portion of the semiconductor channels in the channel region, for example forming a ?-shape cross sectional profile around the semiconductor channel.Type: ApplicationFiled: February 7, 2023Publication date: May 9, 2024Inventors: Kuan-Ting PAN, Kuo-Cheng CHIANG, Shi Ning JU, Chia-Hao CHANG, Chih-Hao WANG
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Publication number: 20240150354Abstract: The present application provides tricyclic urea compounds that modulate the activity of the V617F variant of JAK2, which are useful in the treatment of various diseases, including cancer.Type: ApplicationFiled: August 24, 2023Publication date: May 9, 2024Inventors: Yanran Ai, Onur Atasoylu, Yu Bai, Joseph Barbosa, David M. Burns, Daniel Levy, Brent Douty, Hao Feng, Leah C. Konkol, Cheng-Tsung Lai, Xun Liu, Song Mei, Jun Pan, Haisheng Wang, Liangxing Wu, Wenqing Yao, Eddy W. Yue
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Publication number: 20240127400Abstract: A multi-layer low-pass filter is used to filter a first frame of video data representing at least a portion of an environment of an individual. A first layer of the filter has a first filtering resolution setting for a first subset of the first frame, while a second layer of the filter has a second filtering resolution setting for a second subset. The first subset includes a data element positioned along a direction of a gaze of the individual, and the second subset of the frame surrounds the first subset. A result of the filtering is compressed and transmitted via a network to a video processing engine configured to generate a modified visual representation of the environment.Type: ApplicationFiled: December 13, 2023Publication date: April 18, 2024Applicant: Apple Inc.Inventors: Can Jin, Nicolas Pierre Marie Frederic Bonnier, Hao Pan
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Patent number: 11961763Abstract: Devices and methods that a first gate structure wrapping around a channel layer disposed over the substrate, a second gate structure wrapping around another channel layer disposed over the substrate and a dielectric fin structure formed over a shallow trench isolation (STI) feature and between the first and second gate structures. At least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extends from the first gate structure to the second gate structure.Type: GrantFiled: April 7, 2021Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jia-Chuan You, Kuan-Ting Pan, Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang
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Publication number: 20240120161Abstract: A keyboard device includes plural keycaps, a base plate, plural connecting elements and a circuit board. The plural connecting elements are connected with the respective keycaps and the base plate. The circuit board is located over the base plate. The circuit board includes plural membrane switches and plural first capacitance sensing units. When one of the first capacitance sensing units detects an approaching conductor or detects a motion of the conductor, a driving signal is generated or a control signal is outputted.Type: ApplicationFiled: October 25, 2022Publication date: April 11, 2024Inventors: Chin-Sung Pan, Bo-Hao Su, Chen-Hsuan Hsu
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Publication number: 20240120337Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.Type: ApplicationFiled: January 15, 2023Publication date: April 11, 2024Inventors: Ta-Chun LIN, Chih-Hung HSIEH, Chun-Sheng LIANG, Wen-Chiang HONG, Chun-Wing YEUNG, Kuo-Hua PAN, Chih-Hao CHANG, Jhon Jhy LIAW
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Publication number: 20240116906Abstract: Provided are a GLP-1 receptor agonist compound and a composition and use thereof. The compound can be used for treating or preventing GLP-1 receptor-mediated diseases or disorders and related diseases or disorders.Type: ApplicationFiled: September 13, 2023Publication date: April 11, 2024Inventors: Wenqiang ZHAI, Zhimin ZHANG, Zhe WANG, Hao PAN, Liubin GUO, Qian WANG
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Patent number: 11954011Abstract: An apparatus and a method for executing a customized production line using an artificial intelligence development platform, a computing device and a computer readable storage medium are provided. The apparatus includes: a production line executor configured to generate a native form of the artificial intelligence development platform based on a file set, the native form to be sent to a client accessing the artificial intelligence development platform so as to present a native interactive page of the artificial intelligence development platform; and a standardized platform interface configured to provide an interaction channel between the production line executor and the artificial intelligence development platform. The production line executor is further configured to generate an intermediate result by executing processing logic defined in the file set and to process the intermediate result by interacting with the artificial intelligence development platform via the standardized platform interface.Type: GrantFiled: October 28, 2020Date of Patent: April 9, 2024Assignee: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY CO., LTD.Inventors: Yongkang Xie, Ruyue Ma, Zhou Xin, Hao Cao, Kuan Shi, Yu Zhou, Yashuai Li, En Shi, Zhiquan Wu, Zihao Pan, Shupeng Li, Mingren Hu, Tian Wu
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Publication number: 20240109456Abstract: A method for controlling battery swapping of a vehicle is provided. The vehicle induces a vehicle control unit (VCU), a bidirectional DC-DC converter assembly, a vehicle load, a battery controller, a power battery pack, and a storage battery. The method includes: receiving, by the VCU, a battery swapping instruction when the vehicle is in the high-voltage power-on state; transmitting, by the VCU, a switching instruction to the bidirectional DC-DC converter assembly in response to the battery swapping instruction; and disabling, by the bidirectional DC-DC converter assembly, the buck mode in response to the switching instruction to cut off electrical connection between the power battery pack and a high-voltage circuit of the vehicle by a battery controller, and enabling the boost mode in response to the switching instruction to supply power to the vehicle load by the storage battery through the bidirectional DC-DC converter assembly.Type: ApplicationFiled: December 11, 2023Publication date: April 4, 2024Inventors: Hao LU, Zhicheng TAN, Hongtao SHE, Mingyang GUO, Kangxian PAN
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Publication number: 20240112959Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.Type: ApplicationFiled: December 1, 2023Publication date: April 4, 2024Inventors: Kuan-Ting PAN, Zhi-Chang LIN, Yi-Ruei JHAN, Chi-Hao WANG, Huan-Chieh SU, Shi Ning JU, Kuo-Cheng CHIANG
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Patent number: 11948973Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.Type: GrantFiled: August 16, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Cheng Chiang, Huan-Chieh Su, Shi Ning Ju, Kuan-Ting Pan, Chih-Hao Wang
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Publication number: 20240101956Abstract: The present disclosure discloses a novel strain of Glutamicibacter, derived from insects, which efficiently degrades bifenthrin, belonging to the field of microbial strains. The Glutamicibacter CCTCC NO: M20221445 of the present disclosure was isolated from the intestinal tract of bifenthrin-resistant Ectropis grisescens Warren larvae. It exhibits unique genomic characteristics, growth and phenotypic traits, physiological and biochemical characteristics, as well as the ability to utilize and degrade bifenthrin efficiently. Specifically, it can effectively degrade bifenthrin. Based on phenotypic features, physiological and biochemical characteristics, chemical composition, and molecular biology-based polyphasic classification, Glutamicibacter CCTCC NO: M20221445 is identified as a new species. This bacterium possesses the capability to efficiently degrade bifenthrin, laying the foundation for biological control of E. grisecens and offering new microbial resources to address pesticide residue problems.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Inventors: Yanhua LONG, Xiayu Li, Ting Fang, Hao Gui, Meiqi Wang, Haiyue Wang, Yanru Bao, Anqi Shi, Yuhan Pan, Linlin Zhou, Xiaochun Wan, Yunqiu Yang
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Publication number: 20240105128Abstract: A method for driving an electronic device includes the following steps: receiving a first image data, detecting a first frame rate corresponding to the first image data, generating at least one first scanning signal according to the first image data, receiving a second image data, detecting a second frame rate corresponding to the second image data, and generating at least one second scanning signal according to the second image data. The at least one first scanning signal has a first high voltage level value. The at least one second scanning signal has a second high voltage level value. When the first frame rate is different from the second frame rate, the first high voltage level value is different from the second high voltage level value.Type: ApplicationFiled: August 16, 2023Publication date: March 28, 2024Inventors: Yu-Lin HSIEH, Chien-Hao KUO, Cheng-Shen PAN