Patents by Inventor Hao Wang

Hao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240157832
    Abstract: Examples described herein provide a method that includes receiving, at a vehicle comprising a first battery pack and a second battery pack, at least one of a first electric charge from a first charging station via a first charging port or a second electric charge from a second charging station via a second charging port. The method further includes determining, by a controller of the vehicle, a charging mode of the vehicle. The charging mode is selected from a group consisting of a dynamic balancing during independent multi-port charging mode, a dynamic balancing during independent port charging mode, or a dynamic balancing during parallel charging mode. The method further includes configuring, by the controller of the vehicle, a plurality of switches of a rechargeable energy storage system of the vehicle based at least in part on the determined charging mode.
    Type: Application
    Filed: November 16, 2022
    Publication date: May 16, 2024
    Inventors: Lei Hao, Yue-Yun Wang, Norman K. Bucknor, Venkata Prasad Atluri, Chandra S. Namuduri, Suresh Gopalakrishnan
  • Publication number: 20240158279
    Abstract: A method for manufacturing a microcrystalline glass, the microcrystalline glass manufactured according to the method, and a use thereof are provided. The method includes: (1) nucleation of a raw glass sheet, followed by primary crystallization, where: the primary crystallization temperature is x1, the primary crystallization time is t, and the primary crystallization temperature x1 and the primary crystallization time t satisfy the following conditions: first, ?a×t+652?x1??a×t+667, where a is a constant, 0.1?a?0.25, and tis 10 to 300 min; and second, y1=0.0029x1+b, where y1 is the glass density after primary crystallization, and 2.440 g/cm3?y1?2.490 g/cm3, b is a constant, and 0.55?b?0.60; and (2) secondary crystallization of the glass sheet which has been subject to primary crystallization.
    Type: Application
    Filed: January 26, 2024
    Publication date: May 16, 2024
    Applicant: CHONGQING AUREAVIA HI-TECH GLASS CO., LTD
    Inventors: Hao HUANG, Yubo WANG, Shuang DENG, Baoquan TAN, Wei HU
  • Publication number: 20240162094
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 16, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chuan CHIU, Jia-Chuan YOU, Chia-Hao CHANG, Chun-Yuan CHEN, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
  • Publication number: 20240162227
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The method includes forming a first dielectric feature between first and the second fin structures, wherein each first and second fin structure includes first semiconductor layers and second semiconductor layers alternatingly stacked and in contact with the first dielectric layer. The method also includes removing the second semiconductor layers so that the first semiconductor layers of the first and second fin structures extend laterally from a first side and a second side of the first dielectric feature, respectively, trimming the first dielectric feature so that the first dielectric feature has a reduced thickness on both first and the second sides, and forming a gate electrode layer to surround each of the first semiconductor layers of the first and second fin structures.
    Type: Application
    Filed: November 19, 2023
    Publication date: May 16, 2024
    Inventors: Guan-Lin CHEN, Kuo-Cheng CHIANG, Shi Ning JU, Jung-Chien CHENG, Chih-Hao WANG, Kuan-Lun CHENG
  • Publication number: 20240160469
    Abstract: Embodiments of this specification provide batch scheduling-based application scheduling methods, apparatuses, and systems. In the batch scheduling-based application scheduling method, an application scheduling request is received from a client, where the application scheduling request includes description information used to indicate a chain invoking relationship between applications to be scheduled; the applications to be scheduled are grouped into at least one scheduling object group based on the chain invoking relationship, where applications to be scheduled that are located in the same scheduling object group have the same chain invoking relationship; and the applications to be scheduled are scheduled to a target node by using the scheduling object group as a unit.
    Type: Application
    Filed: November 9, 2023
    Publication date: May 16, 2024
    Inventors: Zaibin HU, Tongkai YANG, Wei WU, Hao DAI, Denghui LI, Jun DU, Zhigang WANG, Weiyu TAN
  • Publication number: 20240159822
    Abstract: A method of measuring chip characteristics includes: outputting an operating voltage to a chip by a test device, wherein the chip comprises a plurality of oscillator circuits configured to generate a plurality of oscillating signals according to the operating voltage; and testing the chip by the test device under a situation that the test device outputs a system clock signal having a first clock period to the chip, including: changing the operating voltage sequentially with the test device until the chip changes from a normal state to a failure state, so as to generate a boundary operating voltage; and recording the plurality of oscillating signals generated according to the boundary operating voltage as measurement data by the test device, wherein the measurement data represents chip characteristics of the chip corresponding to the first clock period.
    Type: Application
    Filed: February 3, 2023
    Publication date: May 16, 2024
    Inventors: Ting-Hao WANG, Pei-Ju LIN
  • Publication number: 20240157819
    Abstract: An electric vehicle, system and method of charging the electric vehicle. In another exemplary embodiment, a system for charging an electric vehicle is disclosed. The system includes a first battery subpack, a second battery subpack, and a processor. The processor is configured to determine a selected battery subpack from the first battery subpack and the second battery subpack for charging based on a comparison of a first state of charge of the first battery subpack a second state of charge of the second battery subpack and connect the selected battery subpack to a corresponding one of a first charge port and a second charge port.
    Type: Application
    Filed: November 14, 2022
    Publication date: May 16, 2024
    Inventors: Chandra S. Namuduri, Suresh Gopalakrishnan, Venkata Prasad Atluri, Lei Hao, Yue-Yun Wang, Ibrahim Haskara
  • Publication number: 20240162797
    Abstract: Disclosed are a voice coil motor a zoom lens and a photography device. The voice coil motor includes a machine shell, a magnet structure, a mover structure and a drive structure. The magnet structure is provided on the machine shell and includes an annular magnetic yoke. The mover structure includes a plurality of mover coils, and the plurality of mover coils are movably sleeved on a yoke section of the annular magnetic yoke. The drive structure includes a plurality of drive chips and the plurality of drive chips are electrically connected to the plurality of mover coils respectively.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 16, 2024
    Applicant: ZHONGSHAN UNION OPTECH RESEARCH INSTITUTE CO., LTD.
    Inventors: Junqiang GONG, Meijiao ZHAO, Shengping QIU, Kun LI, Minde LI, Hao WANG
  • Publication number: 20240162798
    Abstract: Disclosed are a voice coil motor, a zoom lens and a photography device. The voice coil motor includes a machine shell, an annular magnetic yoke, a plurality of magnets and a mover structure. The annular magnetic yoke is provided on the machine shell. The plurality of magnets are provided in the annular magnetic yoke and are provided at interval along a length direction of the annular magnetic yoke. The mover structure includes a mover coil movably sleeved on a yoke section of the annular magnetic yoke.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 16, 2024
    Applicant: ZHONGSHAN UNION OPTECH RESEARCH INSTITUTE CO., LTD.
    Inventors: Junqiang GONG, Meijiao ZHAO, Shengping QIU, Kun LI, Minde LI, Hao WANG
  • Publication number: 20240163204
    Abstract: A multipath aggregation scheduling method and an electronic device provide for configuring transmission sequences of network packets on different paths when there are a plurality of paths between a client and a service end. This enables a network packet sent later on any of the plurality of paths to be sent first on at least one other path, thereby increasing transmission rate of the network.
    Type: Application
    Filed: March 4, 2022
    Publication date: May 16, 2024
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Hao Wang, Zhijun Zhang, Feng Li, Xingmin Guo, Songping Yao
  • Publication number: 20240162743
    Abstract: Disclosed are a power demand side speech interaction method and system. The method includes: obtaining original demand information, the original demand information including user's basic information, user demand information, and a user demand time; converting the original demand information into first information in text format; performing text statistical analysis based on an industry term on the first information in text format, to obtain second information; searching for corresponding user's actual information from a database according to the second information; outputting the user's actual information; searching for a corresponding forecasting model from the database, according to the second information and the user's basic information; calculating, according to a policy limit value of latest policy information in the database, a time for which the model corresponding to the user's basic information reaches the policy limit value; and transmitting an early warning message.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 16, 2024
    Inventors: Bin Yang, Bo Yang, Weitai Kong, Zhi Sun, Jianxin Wang, Wenjun Ruan, Yucheng Ren, Lu Qi, Hao Chen, Yueping Kong, Wei Yu, Hong Li, Guangxi Li, Hao Wu, Xue Sun, Xuewen Sun, Houkai Zhao, Houying Song, Hongxin Yin
  • Publication number: 20240164021
    Abstract: A manufacturing method of an embedded component package structure includes the following steps: providing a carrier and forming a semi-cured first dielectric layer on the carrier, the semi-cured first dielectric layer having a first surface; providing a component on the semi-cured first dielectric layer, and respectively providing heat energies from a top and a bottom of the component to cure the semi-cured first dielectric layer; forming a second dielectric layer on the first dielectric layer to cover the component; and forming a patterned circuit layer on the second dielectric layer, the patterned circuit layer being electrically connected to the component.
    Type: Application
    Filed: January 23, 2024
    Publication date: May 16, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien-Fan CHEN, Chien-Hao WANG
  • Patent number: 11984350
    Abstract: A method includes forming a transistor over a substrate; forming a front-side interconnection structure over the transistor; after forming the front-side interconnection structure, removing the substrate; after removing the substrate, forming a backside via to be electrically connected to the transistor; depositing a dielectric layer to cover the backside via; forming an opening in the dielectric layer to expose the backside via; forming a spacer structure on a sidewall of the opening; after forming a spacer structure, forming a conductive feature in the opening to be electrically connected to the backside via; and after forming the conductive feature, forming an air gap in the spacer structure.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang, Chih-Hao Wang
  • Patent number: 11984488
    Abstract: Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Guan-Lin Chen, Kuo-Cheng Chiang, Shi Ning Ju, Chih-Hao Wang, Kuan-Lun Cheng
  • Patent number: 11983911
    Abstract: Provided is a method and a system for transmitting information. The method is applicable to a processing device, and includes: acquiring a target image of a display device; determining a target area in the target image; and sending display information to the display device, wherein the display information includes information of the target area; wherein the target area is a partial pixel area of the target image, the target area includes pixels with transparencies less than 1, and transparencies of the pixels outside the target area in the target image are all 1.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: May 14, 2024
    Assignees: Beijing BOE Optoelectronics Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Jinghua Miao, Hao Zhang, Lili Chen, Wenyu Li, Qingwen Fan, Xuefeng Wang, Yufan Du
  • Patent number: 11984496
    Abstract: A semiconductor device and a method for manufacturing the same are provided in this disclosure. The semiconductor device includes a semiconductor heterostructure layer. The semiconductor heterostructure layer includes alternating first semiconductor material layers and second semiconductor material layers. Two-dimensional electron gas (2DEG) may be generated between each first semiconductor material layer and adjacent second semiconductor material layer. A conductive structure, including a plurality of conductive fingers extends from a surface of the semiconductor heterostructure layer into the semiconductor heterostructure layer. The plurality of conductive fingers are arranged in a direction substantially parallel to the surface. The lengths of the plurality of conductive fingers progressively increase in that direction so that an end portion of each conductive finger is respectively positioned in a different first semiconductor material layer and is in contact with the 2DEG.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: May 14, 2024
    Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.
    Inventors: Anbang Zhang, King Yuen Wong, Hao Li, Haoning Zheng, Jian Wang
  • Patent number: 11985479
    Abstract: An electronic module is provided. The electronic module includes a first transducer and a second transducer. The first transducer is configured to radiate a first ultrasonic wave. The second transducer is configured to radiate a second ultrasonic wave. The first transducer and the second transducer are disposed on noncoplanar surfaces.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: May 14, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih Lung Lin, Kuei-Hao Tseng, Kai Hung Wang
  • Patent number: 11981666
    Abstract: Provided are a GLP-1 receptor agonist compound and a composition and use thereof. The compound can be used for treating or preventing GLP-1 receptor-mediated diseases or disorders and related diseases or disorders.
    Type: Grant
    Filed: September 13, 2023
    Date of Patent: May 14, 2024
    Assignee: HANGZHOU ZHONGMEIHUADONG PHARMACEUTICAL CO., LTD.
    Inventors: Wenqiang Zhai, Zhimin Zhang, Zhe Wang, Hao Pan, Liubin Guo, Qian Wang
  • Patent number: 11984363
    Abstract: A semiconductor device includes a semiconductor substrate, a first epitaxial feature having a first semiconductor material over the semiconductor substrate, and a second epitaxial feature having a second semiconductor material over the semiconductor substrate. The second semiconductor material being different from the first semiconductor material. The semiconductor device further includes a first silicide layer on the first epitaxial feature, a second silicide layer on the second epitaxial feature, a metal layer on the first silicide layer, a first contact feature over the metal layer, and a second contact feature over the second silicide layer. A first number of layers between the first contact feature and the first epitaxial feature is greater than a second number of layers between the second contact feature and the second epitaxial feature.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
  • Patent number: 11984361
    Abstract: A semiconductor device includes a substrate, a plurality of nanosheets, a plurality of source/drain (S/D) features, and a gate stack. The substrate includes a first fin and a second fin. The first fin has a first width less than a second width of the second fin. The plurality of nanosheets is disposed on the first fin and the second fin. The plurality of source/drain (S/D) features are located on the first fin and the second fin and abutting the plurality of nanosheets. A bottom surface of the plurality of source/drain (S/D) features on the first fin is equal to or lower than a bottom surface of the plurality of source/drain (S/D) features on the second fin. The gate stack wraps each of the plurality of nanosheets.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lo-Heng Chang, Chih-Hao Wang, Kuo-Cheng Chiang, Jung-Hung Chang, Pei-Hsun Wang