Abstract: A distribution statistic is generated for a data block of a memory component based on a reliability statistic for memory cells sampled in the data block. The distribution statistic is indicative of at least one of a uniformity or a non-uniformity of read disturb stress on the sampled memory cells. At least a subset of the data block is relocated to another data block of the memory component in view of the distribution statistic.

Abstract: A first scan operation of a set of memory pages of a data block is performed using a first reliability threshold level to identify a set of scan results. A workload type associated with the data block is determined based on the set of scan results. The first reliability threshold level is adjusted to a second reliability threshold level based on the workload type. A second scan operation of the set of memory pages of the data block is performed using the second reliability threshold level.

Abstract: A processing device in a memory system maintains a counter to track a number of read operations performed on a data block of a memory device and determines that the number of read operations performed on the data block satisfies a first threshold criterion. The processing device further determines whether a number of scan operations performed on the data block satisfies a scan threshold criterion. Responsive to the number of scan operations performed on the data block satisfying the scan threshold criterion, the processing device performs a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first set of wordlines of the data block, the first set comprising first alternating pairs of adjacent wordlines.

Abstract: Storage devices include a memory array comprised of a plurality of memory devices. These memory devices are programmed with a modified distribution across the available memory states within the devices. The modified distribution of memory states attempts to minimize the use of memory states that are susceptible to negative effects. These negative effects can include read and write disturbs as well as data retention errors. Often, these negative effects occur on memory states on the lower and upper states within the voltage threshold range of the memory device. The distribution of memory states can be modified though the use of a modified randomization seed configured to change the probabilities of programming of each page within the memory device. This modification of the randomization seed can yield desired distribution of memory device states that are configured to reduce exposure to negative effects thus prolonging the overall lifespan of the storage device.

Abstract: A processing device in a memory system receives a request to erase a data block of a memory device, determines a number of program/erase cycles performed on the data block, and performs an erase operation to erase the data block. The processing device further determines that the number of program/erase cycles performed on the data block satisfies a scan threshold condition and performs a first threshold voltage integrity scan on the data block to determine a first error rate associated with a current threshold voltage of at least one select gate device of the data block. Responsive to the first error rate associated with the current threshold voltage of the at least one select gate device satisfying an error threshold criterion, the processing device performs a touch up operation on the at least one select gate device to adjust the current threshold voltage to the target threshold voltage.

Abstract: A processing device in a memory system maintains a counter to track a number of read operations performed on a data block of a memory device and determines that the number of read operations performed on the data block satisfies a first threshold criterion. The processing device further determines whether a number of scan operations performed on the data block satisfies a scan threshold criterion. Responsive to the number of scan operations performed on the data block satisfying the scan threshold criterion, the processing device performs a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first set of wordlines of the data block, the first set comprising first alternating pairs of adjacent wordlines.

Abstract: Write operations are performed to write data to user blocks of the memory device and to write, to a first set of purposed blocks, purposed data related to the first data written at the memory device. Whether the first set of purposed blocks satisfy a condition indicating an endurance state of the first set of purposed blocks is determined. Responsive to the first set of purposed blocks satisfies the condition, one or more blocks from a pool of storage area blocks of the memory device are allocated to a second set of purposed blocks.

Abstract: A parity generation operation based on a set of multiple planes of host data is executed to generate a set of multi-page parity data. The set of multi-page parity data is stored in a cache memory of a memory device. A data recovery operation is performed based on the set of multi-page parity data.

Abstract: An example apparatus for garbage collection can include a memory including a plurality of mixed mode blocks. The example apparatus can include a controller. The controller can be configured to write a first portion of sequential host data to the plurality of mixed mode blocks of the memory in a single level cell (SLC) mode. The controller can be configured to write a second portion of sequential host data to the plurality of mixed mode blocks in an XLC mode. The controller can be configured to write the second portion of sequential host data by performing a garbage collection operation. The garbage collection operation can include adding more blocks to a free block pool than a quantity of blocks that are written to in association with writing the second portion of sequential host data to the plurality of mixed mode blocks.

Abstract: A set of memory cells in a data block of a memory component is sampled. A distribution statistic is generated for the data block based on a reliability statistic for each of the set of sampled memory cells. A determination is made based on the distribution statistic of whether the read disturb stress is uniformly or non-uniformly distributed across the data block. In response to a determination that the read disturb stress is non-uniformly distributed across the data block, a first subset of the data block is relocated to another data block of the memory component. The first subset of the data block is associated with a higher concentration of read disturb stress than other subsets of the data block.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including performing a first data integrity check on memory pages of a first set of wordlines of the memory device; performing a second data integrity check on memory pages of a second set of wordlines comprising a plurality of wordlines from the first set of wordlines; identifying, among the first set of wordlines and the second set of wordlines, a wordline having a first data state metric value obtained from the first data integrity check equal to a second data state metric value obtained from the second data integrity check; and performing a third data integrity check on a third set of wordlines comprising at least one wordline from the first set of wordlines, wherein the third data integrity check excludes the identified wordline.

Abstract: A processing device in a memory system receives a first read request from a host system, wherein the first read request is directed to first data stored at a first address in a block of the memory component. The processing device determines that the first address is located within a first region of the block and increments a read counter for the block by a default amount. The processing device further receives a second read request from the host system, wherein the second read request is directed to second data stored at a second address in a block of the memory component, determines that the second address is located within a second region of the block and increments the read counter for the block by a scaled amount.

Abstract: A system includes a memory component and a processing device to determine an amount of data stored at a region of a memory component and determine, based on the amount of data stored in the region of the memory component. The processing device determines a frequency to perform an operation on one or more memory cells of the region of the memory component. The processing device performs the operation on the one or more memory cells at the frequency to maintain the one or more memory cells of the region of the memory component in a first state associated with a first error rate for data stored at the one or more memory cells. The first error rate is less than a second error rate associated with a second state of the one or more memory cells.

Abstract: A first scan operation of a set of memory pages of a data block is performed using a first reliability threshold level to identify a set of scan results. A workload type associated with the data block is determined based on the set of scan results. The first reliability threshold level is adjusted to a second reliability threshold level based on the workload type. A second scan operation of the set of memory pages of the data block is performed using the second reliability threshold level.

Abstract: Host data to be written to a storage area including a set of multiple planes of a memory device is received. A first parity generation operation based on a portion of the set of multiple planes of the host data to generate a set of multi-plane parity data is executed. The set of multi-plane parity data is stored in in a cache memory of a controller of a memory sub-system. A second parity generation operation based on the set of the multiple planes of the host data to generate a set of multi-page parity data is executed. The set of multi-page parity data in the cache memory of the controller of the memory sub-system is stored. A data recovery operation is performed based on the set of multi-plane parity data and the set of multi-page parity data.

Abstract: A memory block of a non-volatile memory device is identified. The memory block has a first region and a second region, where a storage density of the first region is larger than the second region. Data is programmed at the first region of the memory block. An attribute of the memory block based on a sensor is received during programming of the data at the memory block. The attribute characterizes the data being programmed at the first region. The attribute is stored at a volatile during programming of the data at the memory block. The attribute is stored on a memory page of the second region responsive to the programming of the data at the first region being complete.

Abstract: A processing device in a memory system receives a first read request from a host system, wherein the first read request is directed to first data stored at a first address in a block of the memory component. The processing device determines that the first address is located within a first region of the block and increments a read counter for the block by a default amount. The processing device further receives a second read request from the host system, wherein the second read request is directed to second data stored at a second address in a block of the memory component, determines that the second address is located within a second region of the block and increments the read counter for the block by a scaled amount.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including identifying, among a first plurality of wordlines of a set of pages of the memory device, at least one wordline having a current value of a data state metric satisfying a first condition; determining new values of the data state metric of a second plurality of wordlines of the set of pages, wherein the at least one wordline is excluded from the second plurality of wordlines; and responsive to determining that the new values of the data state metric of one or more wordlines of the second plurality of wordlines satisfy a second condition, performing a media management operation with respect to the one or more wordlines.

Abstract: A method includes obtaining a first operation execution time corresponding to an operation performed on a page of a first data unit of a memory device, determining whether the first operation execution time satisfies a condition that is based on a second operation execution time, wherein the second operation execution time is indicative of lack of defect in at least a second data unit of the memory device, and responsive to determining that the first operation execution time satisfies the condition that is based on the second operation execution time, initiating a defect scan operation of at least a subset of pages of the first data unit.

Abstract: parity data storage location. Responsive to determining that a first size of the stored parity data satisfies a first condition, the processing device initiates execution of a compression algorithm to compress the stored parity data. Responsive to determining that a second size of the parity data resulting from the execution of the compression algorithm satisfies a second condition, the processing device performs a scan operation to release at least a subset of the stored parity data.