Abstract: System and method for signal modulation. In one embodiment, a circuit includes a channel for carrying an analog RF signal, a phase offset circuit on the channel, and configured to receive a phase code for modifying the analog RF signal to produce a modified RF signal, and a feedforward cancellation path coupled in parallel to the phase offset circuit for canceling a portion of the modified analog signal.

Abstract: A beamforming system includes a plurality of channelizers and a channel switching module in signal communication with the channelizers. Each channelizer is configured to receive a respective input radio frequency signal and to generate a plurality of respective channels in response to downsampling the respective input radio frequency signal. The channel switching module includes a channel combining circuit configured to selectively combine a common channel generated by each channelizer to form at least one steered analog beam.

Abstract: An electronic warfare (EW) devices and a method of providing jamming techniques are generally described. Firmware is updated by eliminating an existing jamming technique, adding a new technique and/or changing parameters of one of the techniques in the firmware. Changing the technique parameters includes adding a new parameter, deleting an existing parameter, changing the range of values for an existing parameter and changing the order of the parameters to be transmitted by an Operational Flight Program (OFP) to the firmware to generate the technique. The OFP reads a published a register mapping specifying parameters to use in generating the jamming techniques in the EW firmware, a range of the parameters and an order of the parameters. The jamming techniques are generated using parameters transmitted by the OFP to the firmware. The same OFP is used to trigger generation of jamming techniques prior to and after the updating of the firmware.

Abstract: Method and apparatus for leakage signal cancellation in a simultaneous transmit and receive RF system includes: generating a digital transmit signal for transmission from the system; receiving a receive signal produced by reflection of the transmit signal from an object or generated by a second RF system; adaptively filtering the transmit signal by an adaptive finite input response (FIR) filter; calculating filter coefficients for the adaptive FIR filter in real-time at a different sampling rate; adaptively inputting the calculated filter coefficients to the adaptive FIR filter to generate a cancellation signal in real-time; and applying the cancellation signal to the receive signal to cancel leakage in the receive signal to generate an optimum receive signal.

Abstract: A signal identification system includes an analog adaptive channelizer having a plurality of channels. Each channel has a channel size defined by a bandwidth and a gain. The system further includes an electronic signal identification (ID) controller in signal communication with the analog adaptive channelizer. The ID controller is configured to determine a dynamic range event that modifies an energy level of an affected channel among the plurality of channels, and output a feedback signal including channel parameters based on the dynamic range event. The analog adaptive channelizer actively adjusts at least one of the bandwidth and the gain of the affected channel based on the feedback to change the channel size of the affected channel.

Abstract: A method for concurrent transmission of different signal types by a radar system includes: receiving a waveform request for transmitting a first signal type and a second signal type; determining whether the first signal or the second signal is optimized; when the first signal is optimized: transmitting the first and the second signal simultaneously in separate bands; and when the second signal is optimized: determining a time gap between transmission of the second signal, and adjusting pulse repetition interval (PRI) or pulse width of the first signal to fit in the time gap, transmitting the second signal, and transmitting the first signal in the time gap between the transmission of the second signal.

Abstract: There is provided a finite impulse response (FIR) filter for filtering an input voltage signal to generate an output current signal, the FIR filter including a plurality of sample and hold (SH) circuits configured to simultaneously receive the input voltage signal, to sample the input voltage signal at successive sample times according to a sample clock, and to generate a plurality of sampled voltage signals, and a plurality of programmable analog multipliers coupled to the plurality of SH circuits and configured to multiply the plurality of sampled voltage signals by a plurality of binary multiplication factors to generate the output current signal.

Abstract: Devices and methods of providing response pulses in response to threat pulses are general described. The threat pulses are detected, identified and validity determined using reprogrammable firmware. Threat pulses are extracted from memory and the amplitude, frequency, phase, length and timing modified to generate a coherent set of superposed response pulses in response to the threat pulses. The modifications are calculated in situ using parameterization, rather than being based on tables. Multiple response pulses in response to different threat pulses are simultaneously generated, combined and transmitted in a single channel. Partial pulse capability and the capability to create a weighted and modulated composition of multiple response pulses is provided.

Abstract: A system and method for allocating resources receive one or more resource requests describing tasks, each of the one or more resource requests having a request priority, a requested configuration type, and a requestor identifier. In a winner-take-all circuit, all of the existing resource priorities within each configuration of the requested configuration type are compared to determine a highest-priority task occupying each assignment. In a loser-take-all circuit, one or more current highest resource priorities of each configuration within the requested configuration type, which are output from the winner-take-all circuit associated with the requested resource assignment, each of the one or more current resources having a current priority, are compared. One of the one or more current resource configurations within the requested configuration type having the lowest current priority is identified as the lowest-priority current resource configuration.

Abstract: There is provided a programmable multiplier circuit for multiplying an input voltage signal by a binary coefficient, the multiplier circuit including a transconductor including a first amplifying transistor configured to convert the input voltage signal to a current signal, the first amplifying transistor having a gate configured to receive the input voltage signal, and a coefficient multiplier coupled to the transconductor and configured to multiply the current signal by the binary coefficient to generate an amplified current signal.

Abstract: An electronic warfare (EW) devices and a method of providing jamming techniques are generally described. Firmware is updated by eliminating an existing jamming technique, adding a new technique and/or changing parameters of one of the techniques in the firmware. Changing the technique parameters includes adding a new parameter, deleting an existing parameter, changing the range of values for an existing parameter and changing the order of the parameters to be transmitted by an Operational Flight Program (OFP) to the firmware to generate the technique. The OFP reads a published a register mapping specifying parameters to use in generating the jamming techniques in the EW firmware, a range of the parameters and an order of the parameters. The jamming techniques are generated using parameters transmitted by the OFP to the firmware. The same OFP is used to trigger generation of jamming techniques prior to and after the updating of the firmware.

Abstract: A butterfly channelizer includes at least two stages. Each stage includes at least one dual-channel module configured to convert an input time domain signal into a second time domain signal of lower bandwidth. At least one clock is configured to generate a clock signal that drives the at least two stages. A first stage has a first number of dual-channel modules and a second stage following the first stage has a second number of dual-channel modules greater than the first number.

Abstract: There is provided a programmable multiplier circuit for multiplying an input voltage signal by a binary coefficient, the multiplier circuit including a transconductor including a first amplifying transistor configured to convert the input voltage signal to a current signal, the first amplifying transistor having a gate configured to receive the input voltage signal, and a coefficient multiplier coupled to the transconductor and configured to multiply the current signal by the binary coefficient to generate an amplified current signal.

Abstract: There is provided a programmable multiplier circuit for multiplying an input voltage signal by a binary coefficient, the multiplier circuit including a transconductor including a first amplifying transistor configured to convert the input voltage signal to a current signal, the first amplifying transistor having a gate configured to receive the input voltage signal, and a coefficient multiplier coupled to the transconductor and configured to multiply the current signal by the binary coefficient to generate an amplified current signal.

Abstract: There is provided a finite impulse response (FIR) filter for filtering an input voltage signal to generate an output current signal, the FIR filter including a plurality of sample and hold (SH) circuits configured to simultaneously receive the input voltage signal, to sample the input voltage signal at successive sample times according to a sample clock, and to generate a plurality of sampled voltage signals, and a plurality of programmable analog multipliers coupled to the plurality of SH circuits and configured to multiply the plurality of sampled voltage signals by a plurality of binary multiplication factors to generate the output current signal.

Abstract: An electronic analog memory system includes at least one analog programmable delay module configured to receive an input radio frequency pulse. The analog programmable delay module generates a time delayed output signal in response to applying at least one time delay to the input radio frequency pulse. A switching module is configured to selectively deliver the time delayed output signal to an output of the electronic analog memory system. The electronic analog memory system further includes an activity detector module configured to determine the amplitude of the input radio frequency pulse. The activity detector module also controls the switching module to deliver the time delayed output signal to the output in response to the at least one amplitude exceeding an amplitude threshold.

Abstract: A system includes a library of elements to create a model describing a waveform parameter technique. A constraint checker verifies that the created model is correct by construction by needing no verification after compilation. The constraint checker also implements a valid programmable device build according to the waveform parameter technique. A placement decision module receives the verified models produces a placement decision for placing the waveform parameter technique based on the verified model in a programmable device. A synthesis tool receives the verified model from the placement decision module and synthesizes the waveform parameter technique based on the verified model. A link/loader receives the placement decision from the placement decision module and receives the synthesized technique from the synthesis tool. The link/loader also places the waveform parameter technique in the programmable device according to the placement decision.

Abstract: Generally discussed herein are systems, apparatuses, and methods for generating a replica of a first signal with a notch at one or more desired frequencies. In an example, an apparatus can include a pulse cataloger configured to analyze the first signal and to provide phase modulation information about the first signal, a direct digital synthesizer having an output and configured to modulate a second signal using the phase modulation information and to provide the second signal at the output. The second signal can include a representation of the first signal with a frequency notch at a particular center frequency within the bandwidth of the second signal.

Abstract: Embodiments are directed to operating an analog signal processing circuit to emulate a Rotman lens. The analog signal processing circuit applies a plurality of time delays to a plurality of signals associated with a plurality of beam ports. The analog signal processing circuit forms a plurality of output beams for transmission by a plurality of array ports included in an array based on the time delayed signals by summing the time delayed signals. The time delays are based on a direction of transmission of the output beams.

Abstract: Embodiments are directed to a channelizer architecture configured to provide fully configurable frequency spectrum shaping by: establishing a plurality of parameters of the architecture, receiving an input signal, processing, by the architecture, the input signal in accordance with the plurality of parameters to obtain an output signal, analyzing the output signal to detect an object, and modifying the plurality of parameters to account for at least one dynamic condition associated with the object.