Patents by Inventor Harry J. Levinson
Harry J. Levinson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6593035Abstract: A pellicle utilizes a thin film attached to a frame. The film is relatively transparent to radiation. The frame is coupled to a periphery of the film and is exclusive of the center portion of the film. The pellicle can be manufactured by growing a relatively transparent film on a silicon substrate and removing the substrate to expose at least a portion of the relatively transparent film.Type: GrantFiled: January 26, 2001Date of Patent: July 15, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Harry J. Levinson, Christopher F. Lyons
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Patent number: 6556286Abstract: An inspection tool or inspection system can be utilized to determine whether the appropriate pattern is on a reticle. The reticle can be associated with EUV lithographic tools. The system utilizes an at least two wavelengths of light. The light is directed to the reticle at the at least two wavelengths of light.Type: GrantFiled: April 30, 2001Date of Patent: April 29, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Bruno M. La Fontaine, Harry J. Levinson, Jongwook Kye
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Patent number: 6544693Abstract: A pellicle utilizes a thin film attached to a substrate. The film is relatively transparent to radiation. The substrate is coupled to a periphery of the film and is exclusive of the center portion of the film. The pellicle can be manufactured by growing a relatively transparent film on a substrate and etching the substrate to expose a portion of the relatively transparent film.Type: GrantFiled: January 26, 2001Date of Patent: April 8, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Harry J. Levinson, Christopher F. Lyons
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Patent number: 6544885Abstract: A method of forming a conductor pattern on a base with uneven topography includes placing conductor material on the base, placing a hard mask material on the conductor material, planarizing an exposed surface of the hard mask material, and placing a layer of resist on the hard mask material. The resist is patterned and the patterned resist is used in selectively etching the hard mask material, with the hard mask material used in selectively etching the underlying conductor material. By planarizing the hard mask material prior to placing a layer of resist thereupon, uniformity of the resist coating is enhanced and depth of focus problems in exposing the resist are reduced.Type: GrantFiled: November 3, 2000Date of Patent: April 8, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Khanh B. Nguyen, Harry J. Levinson, Christopher F. Lyons, Scott A. Bell, Fei Wang, Chih Yuh Yang
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Publication number: 20020139773Abstract: A process for forming sub-lithographic features in an integrated circuit is disclosed herein. The process includes modifying a photoresist layer after patterning and development but before it is utilized to pattern the underlying layers. The modified photoresist layer has different etch rates in the vertical and horizontal directions. The modified photoresist layer is trimmed with a plasma etch. A feature included in the trimmed photoresist layer has a sub-lithographic lateral dimension.Type: ApplicationFiled: March 28, 2001Publication date: October 3, 2002Applicant: Advanced Micro Devices, Inc.Inventors: Calvin T. Gabriel, Harry J. Levinson, Uzodinma Okoroanyanwu
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Publication number: 20020132171Abstract: The present invention provides a method of and system for reducing the absorption of light by opaque material in a photomask. The method includes providing a photomask substrate, and applying an opaque material to one side of the photomask substrate. The interface between the opaque material and photomask substrate reflects at least 80 percent of the light through the photomask.Type: ApplicationFiled: December 20, 2000Publication date: September 19, 2002Applicant: Advanced Micro Devices, Inc.Inventors: Harry J. Levinson, Fan Piao, Christopher A. Spence
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Publication number: 20020127477Abstract: A pellicle utilizes a thin film attached to a substrate. The film is relatively transparent to radiation. The substrate is coupled to a periphery of the film and is exclusive of the center portion of the film. The pellicle can be manufactured by growing a relatively transparent film on a substrate and etching the substrate to expose a portion of the relatively transparent film.Type: ApplicationFiled: January 26, 2001Publication date: September 12, 2002Applicant: Advanced Micro Devices, Inc..Inventors: Harry J. Levinson, Christopher F. Lyons
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Patent number: 6440640Abstract: A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transition metal layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the transition metal layer. The first etch step includes an etch chemistry that is selective to the transition metal layer over the ultra-thin photoresist layer and the dielectric layer. The transition metal layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.Type: GrantFiled: October 31, 2000Date of Patent: August 27, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Chih Yuh Yang, Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Fei Wang, Scott A. Bell
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Publication number: 20010038972Abstract: A method of forming a shallow trench isolation is provided. In the method, a barrier oxide layer is formed on a substrate, and a silicon nitride layer is formed on the barrier oxide layer. A metal layer is formed on the silicon nitride layer, and an ultra-thin photoresist is formed on the metal layer. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a shallow trench. The ultra-thin photoresist layer is used as a mask during a first etch step to transfer the shallow trench pattern to the metal layer. The first etch step includes an etch chemistry that is selective to the metal layer over the ultra-thin photoresist layer. The metal layer is used as a hard mask during a second etch step to form the shallow trench by etching portions of the silicon nitride layer, barrier oxide layer and substrate.Type: ApplicationFiled: November 20, 1998Publication date: November 8, 2001Applicant: Christopher F. LyonsInventors: CHRISTOPHER F. LYONS, SCOTT A. BELL, HARRY J. LEVINSON, KHANH B. NGUYEN, FEI WANG, CHIH YUH YANG
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Patent number: 6309926Abstract: A method of forming a gate structure is provided. In the method, a nitride layer is formed on a gate material layer. An ultra-thin photoresist layer is formed on the nitride layer. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for the gate. The ultra-thin photoresist layer is used as a mask during a first etch step to transfer the gate pattern to the nitride layer. The first etch step includes an etch chemistry that is selective to the nitride layer over the ultra-thin photoresist layer. The nitride layer is used as a hard mask during a second etch step to form the gate by transferring the gate pattern to the gate material layer via the second etch step.Type: GrantFiled: December 4, 1998Date of Patent: October 30, 2001Assignee: Advanced Micro DevicesInventors: Scott A. Bell, Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Fei Wang, Chih Yuh Yang
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Patent number: 6306560Abstract: In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon oxynitride layer over the oxide layer; depositing an ultra-thin photoresist over the silicon oxynitride layer, the ultra-thin photoresist having a thickness less than about 2,000 Å; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon oxynitride layer; etching the exposed portion of the silicon oxynitride layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.Type: GrantFiled: December 2, 1998Date of Patent: October 23, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Fei Wang, Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih Yuh Yang
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Publication number: 20010014512Abstract: In one embodiment, the present invention relates to a method of forming a shallow trench, involving the steps of providing a semiconductor substrate comprising a barrier oxide layer over at the semiconductor substrate and a nitride layer over the barrier oxide layer; depositing an ultra-thin photoresist over the nitride layer, the ultra-thin photoresist having a thickness of about 2,000 Å or less; patterning the ultra-thin photoresist to expose a portion of the nitride layer and to define a pattern for the shallow trench; etching the exposed portion of the nitride layer with an etchant having a nitride:photoresist selectivity of at least about 10:1 to expose a portion of the barrier oxide layer; etching the exposed portion of the barrier oxide layer to expose a portion of the semiconductor substrate; and etching the exposed portion of the semiconductor substrate to provide the shallow trench.Type: ApplicationFiled: September 17, 1999Publication date: August 16, 2001Inventors: CHRISTOPHER F. LYONS, SCOTT A. BELL, HARRY J. LEVINSON, KHANH B. NGUYEN, FEI WANG, CHIH YUH YANG
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Patent number: 6251545Abstract: The present invention provides a method and system for improving the transmission of light through a photomask. The method includes providing a photomask substrate, and applying at least one anti-reflection coating to at least one side of the photomask substrate. The anti-reflection coating reduces the loss of light during lithography due to reflections. This increases the efficiency of the lithography. The method and system has the added advantage of reducing the amount of undesired exposure of a photoresist.Type: GrantFiled: July 20, 1999Date of Patent: June 26, 2001Assignee: Advanced Micro Devices, Inc.Inventor: Harry J. Levinson
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Patent number: 6200907Abstract: In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a barrier metal layer over the oxide layer; depositing an ultra-thin photoresist over the barrier metal layer, the ultra-thin photoresist having a thickness less than about 2,000 Å; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the barrier metal layer; etching the exposed portion of the barrier metal layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.Type: GrantFiled: December 2, 1998Date of Patent: March 13, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Fei Wang, Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih Yuh Yang
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Patent number: 6184128Abstract: In one embodiment, the present invention relates to a dual damascene method involving the steps of providing a substrate having a first low k material layer; forming a first hard mask layer over the first low k material layer; patterning a first opening having a first width in the first hard mask layer using a first photoresist thereby exposing a portion of the first low k material layer; removing the first photoresist; depositing a second low k material layer over the patterned first hard mask layer and the exposed portion of the first low k material layer; forming a second hard mask layer over the second low k material layer; patterning a second opening having a width larger than the first width in the second hard mask layer using a second photoresist thereby exposing a portion of the second low k material layer; anisotropically etching the exposed portions of the first and second low k material layers; and removing the second photoresist, wherein and at least one of the first photoresist and the second phoType: GrantFiled: January 31, 2000Date of Patent: February 6, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Fei Wang, Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih Yuh Yang
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Patent number: 6171763Abstract: In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, a silicon nitride layer over the metal layer, and an oxide layer over the silicon nitride layer; depositing an ultra-thin photoresist over the oxide layer, the ultra-thin photoresist having a thickness less than about 2,000 Å; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the silicon nitride layer; etching the exposed portion of the silicon nitride layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.Type: GrantFiled: December 2, 1998Date of Patent: January 9, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Fei Wang, Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih Yuh Yang
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Patent number: 6165695Abstract: A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and an amorphous silicon layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the amorphous silicon layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the amorphous silicon layer. The first etch step includes an etch chemistry that is selective to the amorphous silicon layer over the ultra-thin photoresist layer and the dielectric layer. The amorphous silicon layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.Type: GrantFiled: December 1, 1998Date of Patent: December 26, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Chih Yuh Yang, Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Fei Wang, Scott A. Bell
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Patent number: 6162587Abstract: A method of forming a via structure is provided. In the method, a dielectric layer is formed on an anti-reflective coating (ARC) layer covering a first metal layer; and a transition metal layer is formed on the dielectric layer. An ultra-thin photoresist layer is formed on the transition metal layer, and the ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern for a via. The patterned ultra-thin photoresist layer is used as a mask during a first etch step to transfer the via pattern to the transition metal layer. The first etch step includes an etch chemistry that is selective to the transition metal layer over the ultra-thin photoresist layer and the dielectric layer. The transition metal layer is employed as a hard mask during a second etch step to form a contact hole corresponding to the via pattern by etching portions of the dielectric layer.Type: GrantFiled: December 1, 1998Date of Patent: December 19, 2000Assignee: Advanced Micro DevicesInventors: Chih Yuh Yang, Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Fei Wang, Scott A. Bell
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Patent number: 6156658Abstract: In one embodiment, the present invention relates to a method of forming a metal line, involving the steps of providing a semiconductor substrate comprising a metal layer, an oxide layer over the metal layer, and a silicon layer over the oxide layer; depositing an ultra-thin photoresist over the silicon layer, the ultra-thin photoresist having a thickness less than about 2,000 .ANG.; irradiating the ultra-thin photoresist with electromagnetic radiation having a wavelength of about 250 nm or less; developing the ultra-thin photoresist exposing a portion of the silicon layer; etching the exposed portion of the silicon layer exposing a portion of the oxide layer; etching the exposed portion of the oxide layer exposing a portion of the metal layer; and etching the exposed portion of the metal layer thereby forming the metal line.Type: GrantFiled: December 2, 1998Date of Patent: December 5, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Fei Wang, Christopher F. Lyons, Khanh B. Nguyen, Scott A. Bell, Harry J. Levinson, Chih Yuh Yang
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Patent number: 6140023Abstract: A lithographic process for fabricating sub-micron features is provided. A silicon containing ultra-thin photoresist is formed on an underlayer surface to be etched. The ultra-thin photoresist layer is patterned with short wavelength radiation to define a pattern. The ultra-thin photoresist is oxidized so as to convert the silicon therein to silicon dioxide. The oxidized ultra-thin photoresist layer is used as a hard mask during an etch step to transfer the pattern to the underlayer. The etch step includes an etch chemistry that is highly selective to the underlayer over the oxidized ultra-thin photoresist layer.Type: GrantFiled: December 1, 1998Date of Patent: October 31, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Harry J. Levinson, Scott A. Bell, Christopher F. Lyons, Khanh B. Nguyen, Fei Wang, Chih Yuh Yang