Patents by Inventor Haruka Shimizu
Haruka Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9041049Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.Type: GrantFiled: August 19, 2013Date of Patent: May 26, 2015Assignee: Renesas Electronics CorporationInventors: Koichi Arai, Yasuaki Kagotoshi, Nobuo Machida, Natsuki Yokoyama, Haruka Shimizu
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Publication number: 20150075611Abstract: Provided is a novel CaS-based phosphor with which chemical reactions can be inhibited even if said CaS-based phosphor is heated with a heterogeneous material. This phosphor includes: a crystalline parent material represented by the composition formula Ca1-xSrxS.yZnO (in the formula, 0?x<1, 0<y?0.5); and a luminescent center.Type: ApplicationFiled: October 22, 2013Publication date: March 19, 2015Applicant: Mitsui Mining & Smelting Co., Ltd.Inventors: Masaaki Inamura, Michiyo Inoue, Akinori Kumagai, Haruka Shimizu, Takayoshi Mori, Jun-ichi Itoh
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Publication number: 20150060887Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.Type: ApplicationFiled: November 9, 2014Publication date: March 5, 2015Inventors: Koichi Arai, Yasuaki Kagotoshi, Nobuo Machida, Natsuki Yokoyama, Haruka Shimizu
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Publication number: 20150041829Abstract: A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.Type: ApplicationFiled: September 24, 2014Publication date: February 12, 2015Inventors: Haruka SHIMIZU, Natsuki YOKOYAMA
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Patent number: 8890169Abstract: On a front surface of a region where a junction termination extension structure of a semiconductor device using silicon carbide is formed, a structure having an n-type semiconductor region with a concentration relatively higher than a concentration of an n?-type drift layer is formed. An edge of the junction termination extension structure located on a side away from an active region is surrounded from its bottom surface to its front surface by an n-type semiconductor region. By this means, it is possible to provide a device with a low resistance while ensuring a withstand voltage, or by decreasing the resistance of the device, it is possible to provide a device with low power loss.Type: GrantFiled: November 8, 2010Date of Patent: November 18, 2014Assignee: Hitachi, Ltd.Inventors: Norifumi Kameshiro, Haruka Shimizu
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Patent number: 8872191Abstract: A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.Type: GrantFiled: October 18, 2012Date of Patent: October 28, 2014Assignee: Renesas Electronics CorporationInventors: Haruka Shimizu, Natsuki Yokoyama
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Publication number: 20140284625Abstract: A manufacturing method of a junction field effect transistor includes the steps of: (a) forming an n+-type source layer on a surface of an n?-type drift layer formed on an n+-type SiC substrate; (b) forming a plurality of shallow trenches disposed at predetermined intervals by etching the surface of the n?-type drift layer with a silicon oxide film formed on the n?-type drift layer used as a mask; (c) forming an n-type counter dope layer by doping the n?-type drift layer below each of the shallow trenches with nitrogen by using a vertical ion implantation method; (d) forming a sidewall spacer on each sidewall of the silicon oxide film and the shallow trenches; and (e) forming a p-type gate layer by doping the n?-type drift layer below each of shallow trenches with aluminum by using the vertical ion implantation method.Type: ApplicationFiled: March 20, 2014Publication date: September 25, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Yasuaki KAGOTOSHI, Koichi ARAI, Natsuki YOKOYAMA, Haruka SHIMIZU
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Publication number: 20140196763Abstract: In order to provide a novel CaS:Eu series red phosphor in which moisture-resistance has been improved, a red phosphor is proposed, containing Ba at 0.001 to 1.00 mol % with respect to CaS in a red phosphor represented by the general formula: CaS:Eu.Type: ApplicationFiled: August 7, 2012Publication date: July 17, 2014Applicant: MITSUI MINING & SMELTING CO., LTD.Inventors: Asuka Sasakura, Jun-ichi Itoh, Masaaki Inamura, Akinori Kumagai, Haruka Shimizu
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Patent number: 8766277Abstract: The leakage current generated in a pn junction region between a gate and a source is reduced in a junction FET using a silicon carbide substrate. In a trench junction FET using a silicon carbide substrate, nitrogen is introduced into a sidewall and a bottom surface of a trench, thereby forming an n type layer and an n+ type layer on a surface of the trench. In this manner, the pn junction region corresponding to the junction region between a p+ type gate region and an n+ type source region is exposed on a main surface of a semiconductor substrate instead of on the damaged sidewall of the trench, and also the exposed region thereof is narrowed. Accordingly, the leakage current in the pn junction region can be reduced.Type: GrantFiled: February 3, 2011Date of Patent: July 1, 2014Assignee: Renesas Electronics CorporationInventors: Haruka Shimizu, Natsuki Yokoyama
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Publication number: 20140021502Abstract: A highly reliable light-emitting device is provided, which is capable of effectively suppressing detrimental effects of sulfuric gas. A light-emitting device comprising a solid light-emitting element 1, a metal member 2 reacting with sulfuric gas and a phosphor-containing layer 5 that contains a phosphor 3, the phosphor-containing layer 5 containing a sulfuric gas-adsorbing substance 4 that adsorbs sulfuric gas, and, when the phosphor-containing layer 5 is tripartitioned from the side near the metal member to far into a proximal layer portion, an intermediate layer portion and an outer layer portion, the concentration of sulfuric gas-adsorbing substance 4 in the proximal layer portion is made to be higher than those for the intermediate layer portion and the outer layer portion.Type: ApplicationFiled: February 22, 2012Publication date: January 23, 2014Applicant: MITSUI MINING & SMELTING CO., LTD.Inventors: Haruka Shimizu, Masaaki Inamura, Asuka Sasakura, Akinori Kumagai
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Publication number: 20130334542Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.Type: ApplicationFiled: August 19, 2013Publication date: December 19, 2013Applicant: Renesas Electronics CorporationInventors: Koichi ARAI, Yasuaki KAGOTOSHI, Nobuo MACHIDA, Natsuki YOKOYAMA, Haruka SHIMIZU
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Publication number: 20130285071Abstract: On a front surface of a region where a junction termination extension structure of a semiconductor device using silicon carbide is formed, a structure having an n-type semiconductor region with a concentration relatively higher than a concentration of an n?-type drift layer is formed. An edge of the junction termination extension structure located on a side away from an active region is surrounded from its bottom surface to its front surface by an n-type semiconductor region. By this means, it is possible to provide a device with a low resistance while ensuring a withstand voltage, or by decreasing the resistance of the device, it is possible to provide a device with low power loss.Type: ApplicationFiled: November 8, 2010Publication date: October 31, 2013Inventors: Norifumi Kameshiro, Haruka Shimizu
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Patent number: 8564060Abstract: There is no effective method for fabricating a semiconductor power device containing UMOSFET possessing large channel mobility and whose threshold voltage can be lowered with no loss in blocking voltage. A semiconductor device with large blocking voltage is provided utilizing silicon carbide trench MOSFET possessing both narrow regions where the p body concentration is low, and wide regions where the p body concentration is high.Type: GrantFiled: July 12, 2010Date of Patent: October 22, 2013Assignee: Hitachi, Ltd.Inventors: Haruka Shimizu, Natsuki Yokoyama
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Patent number: 8524552Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.Type: GrantFiled: January 31, 2012Date of Patent: September 3, 2013Assignee: Renesas Electronics CorporationInventors: Koichi Arai, Yasuaki Kagotoshi, Nobuo Machida, Natsuki Yokoyama, Haruka Shimizu
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Patent number: 8436397Abstract: In a junction FET of a normally-off type, a technique capable of achieving both of improvement of a blocking voltage and reduction of an ON resistance is provided. In a junction FET using silicon carbide as a substrate material, impurities are doped to a vicinity of a p-n junction between a gate region and a channel-formed region, the impurities having a conductive type which is reverse to that of impurities doped in the gate region and same as that of impurities doped in the channel-formed region. In this manner, an impurity profile of the p-n junction becomes abrupt, and further, an impurity concentration of a junction region forming the p-n junction with the gate region in the channel-formed region is higher than those of a center region in the channel-formed region and of an epitaxial layer.Type: GrantFiled: December 16, 2009Date of Patent: May 7, 2013Assignee: Renesas Electronics CorporationInventors: Haruka Shimizu, Natsuki Yokoyama
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Publication number: 20130056754Abstract: A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.Type: ApplicationFiled: October 18, 2012Publication date: March 7, 2013Inventors: Haruka SHIMIZU, Natsuki YOKOYAMA
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Patent number: 8390001Abstract: A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.Type: GrantFiled: March 8, 2011Date of Patent: March 5, 2013Assignee: Renesas Electronics CorporationInventors: Haruka Shimizu, Natsuki Yokoyama
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Publication number: 20120193641Abstract: In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times.Type: ApplicationFiled: January 31, 2012Publication date: August 2, 2012Inventors: Koichi Arai, Yasuaki Kagotoshi, Nobuo Machida, Natsuki Yokoyama, Haruka Shimizu
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Patent number: 8049223Abstract: A junction FET having a large gate noise margin is provided. The junction FET comprises an n? layer forming a drift region of the junction FET formed over a main surface of an n+ substrate made of silicon carbide, a p+ layer forming a gate region formed in contact with the n? layer forming the drift region and a gate electrode provided in an upper layer of the n+ substrate. The junction FET further incorporates pn diodes formed over the main surface of the n+ substrate and electrically connecting the p+ layer forming the gate region and the gate electrode.Type: GrantFiled: May 25, 2008Date of Patent: November 1, 2011Assignee: Renesas Electronics CorporationInventors: Haruka Shimizu, Hidekatsu Onose
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Publication number: 20110220916Abstract: A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.Type: ApplicationFiled: March 8, 2011Publication date: September 15, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Haruka SHIMIZU, Natsuki YOKOYAMA