Patents by Inventor Haruka Shimizu

Haruka Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110198613
    Abstract: The leakage current generated in a pn junction region between a gate and a source is reduced in a junction FET using a silicon carbide substrate. In a trench junction FET using a silicon carbide substrate, nitrogen is introduced into a sidewall and a bottom surface of a trench, thereby forming an n type layer and an n+ type layer on a surface of the trench. In this manner, the pn junction region corresponding to the junction region between a p+ type gate region and an n+ type source region is exposed on a main surface of a semiconductor substrate instead of on the damaged sidewall of the trench, and also the exposed region thereof is narrowed. Accordingly, the leakage current in the pn junction region can be reduced.
    Type: Application
    Filed: February 3, 2011
    Publication date: August 18, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Haruka SHIMIZU, Natsuki YOKOYAMA
  • Patent number: 7880174
    Abstract: An object of the present invention is to reduce the conducting loss of an existing conversion circuit while suppressing its noise. The present invention is typically a circuit arrangement includes at least one switching device and a free-wheel diode connected in parallel with the switching device. The free-wheel diode is formed by connecting a silicon PiN diode in parallel with a Schottky barrier diode that uses a semiconductor material having a wider band gap than silicon as a base material. The silicon PiN diode and Schottky barrier diode are separate chips.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: February 1, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Haruka Shimizu, Katsumi Ishikawa, Masahiro Nagasu, Dai Tsugawa
  • Publication number: 20110018004
    Abstract: There is no effective method for fabricating a semiconductor power device containing UMOSFET possessing large channel mobility and whose threshold voltage can be lowered with no loss in blocking voltage. A semiconductor device with large blocking voltage is provided utilizing silicon carbide trench MOSFET possessing both narrow regions where the p body concentration is low, and wide regions where the p body concentration is high.
    Type: Application
    Filed: July 12, 2010
    Publication date: January 27, 2011
    Inventors: Haruka SHIMIZU, Natsuki Yokoyama
  • Patent number: 7772613
    Abstract: A normally-off type junction FET in which a channel resistance is reduced without lowering its blocking voltage is provided. In a junction FET formed with using a substrate made of silicon carbide, an impurity concentration of a channel region (second epitaxial layer) is made higher than an impurity concentration of a first epitaxial layer to be a drift layer. The channel region is formed of a first region in which a channel width is constant and a second region below the first region in which the channel width becomes wider toward the drain (substrate) side. A boundary between the first epitaxial layer and the second epitaxial layer is positioned in the second region in which the channel width becomes wider toward the drain (substrate) side.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: August 10, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Haruka Shimizu, Natsuki Yokoyama
  • Publication number: 20100163935
    Abstract: In a junction FET of a normally-off type, a technique capable of achieving both of improvement of a blocking voltage and reduction of an ON resistance is provided. In a junction FET using silicon carbide as a substrate material, impurities are doped to a vicinity of a p-n junction between a gate region and a channel-formed region, the impurities having a conductive type which is reverse to that of impurities doped in the gate region and same as that of impurities doped in the channel-formed region. In this manner, an impurity profile of the p-n junction becomes abrupt, and further, an impurity concentration of a junction region forming the p-n junction with the gate region in the channel-formed region is higher than those of a center region in the channel-formed region and of an epitaxial layer.
    Type: Application
    Filed: December 16, 2009
    Publication date: July 1, 2010
    Inventors: Haruka Shimizu, Natsuki Yokoyama
  • Publication number: 20100025739
    Abstract: A normally-off type junction FET in which a channel resistance is reduced without lowering its blocking voltage is provided. In a junction FET formed with using a substrate made of silicon carbide, an impurity concentration of a channel region (second epitaxial layer) is made higher than an impurity concentration of a first epitaxial layer to be a drift layer. The channel region is formed of a first region in which a channel width is constant and a second region below the first region in which the channel width becomes wider toward the drain (substrate) side. A boundary between the first epitaxial layer and the second epitaxial layer is positioned in the second region in which the channel width becomes wider toward the drain (substrate) side.
    Type: Application
    Filed: July 31, 2009
    Publication date: February 4, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Haruka SHIMIZU, Natsuki YOKOYAMA
  • Publication number: 20090168471
    Abstract: A circuit device includes at least one switching element and a free wheeling diode connected in parallel to the switching element. The free wheeling diode is made up of a Schottky barrier diode using a semiconductor material having a band gap larger than silicon as its base material and also a silicon PiN diode, which are connected in parallel. The Schottky barrier diode and the silicon PiN diode are provided in the form of separate chips. A circuit system is also provided wherein a diode having a Schottky junction of a compound semiconductor as a rectification element built therein is combined, and a relationship, R2>4L/C, with impedance R (resistance), L (inductance), and C (capacitance) determined by a closed circuit between a power source and a positive or negative terminal when the current of the diode becomes zero during recovery operation, is satisfied.
    Type: Application
    Filed: December 23, 2008
    Publication date: July 2, 2009
    Inventors: Dai Tsugawa, Katsumi Ishikawa, Masahiro Nagasu, Haruka Shimizu
  • Patent number: 7498460
    Abstract: The present invention relates to isophthalic acid derivatives, to a process for their preparation and to their use for producing medicaments for the treatment and/or prophylaxis of diseases in humans and animals, in particular of cardiovascular disorders.
    Type: Grant
    Filed: November 28, 2003
    Date of Patent: March 3, 2009
    Assignee: Bayer Healthcare AG
    Inventors: Michael Härter, Jens Ergüden, Frank Wunder, Hanna Tinel, Johannes Köbberling, Eva-Maria Becker, Klaus Münter, Karl-Heinz Schlemmer, Raimund Kast, Peter Kolkhof, Gunter Karig, Lars Bärfacker, Walter Hübsch, Joachim Schuhmacher, Susanne Zuleger, Arnel Concepcion, Haruka Shimizu
  • Publication number: 20090014719
    Abstract: A junction FET having a large gate noise margin is provided. The junction FET comprises an n? layer forming a drift region of the junction FET formed over a main surface of an n+ substrate made of silicon carbide, a p+ layer forming a gate region formed in contact with the n? layer forming the drift region and a gate electrode provided in an upper layer of the n+ substrate. The junction FET further incorporates pn diodes formed over the main surface of the n+ substrate and electrically connecting the p+ layer forming the gate region and the gate electrode.
    Type: Application
    Filed: May 25, 2008
    Publication date: January 15, 2009
    Inventors: Haruka Shimizu, Hidekatsu Onose
  • Publication number: 20080258252
    Abstract: An object of the present invention is to reduce the conducting loss of an existing conversion circuit while suppressing its noise. The present invention is typically a circuit arrangement includes at least one switching device and a free-wheel diode connected in parallel with the switching device. The free-wheel diode is formed by connecting a silicon PiN diode in parallel with a Schottky barrier diode that uses a semiconductor material having a wider band gap than silicon as a base material. The silicon PiN diode and Schottky barrier diode are separate chips.
    Type: Application
    Filed: February 12, 2008
    Publication date: October 23, 2008
    Inventors: Haruka Shimizu, Katsumi Ishikawa, Masahiro Nagasu, Dai Tsugawa
  • Publication number: 20060166989
    Abstract: The present invention relates to 2-naphthamides, which are useful as an active ingredient of pharmaceutical preparations. The 2-naphthamides of the present invention have IP receptor antagonistic activity, and can be used for the prophylaxis and treatment of diseases associated with IP receptor activity. Such diseases include urological diseases or disorder as follows: bladder outlet obstruction, overactive bladder, urinary incontinence, detrusor hyper-reflexia, detrusor instability, reduced bladder capacity, frequency of micturition, urge incontinence, stress incontinence, bladder hyperreactivity, benign prostatic hypertrophy (BPH), pro-statitis, urinary frequency, nocturia, urinary urgency, pelvic hypersensitivity, urethritis, pelvic pain syndrome, prostatodynia, cystitis, or idiophatic bladder hypersensitivity.
    Type: Application
    Filed: May 30, 2003
    Publication date: July 27, 2006
    Applicant: Bayer Healthcare AG
    Inventors: Makoto Shimazaki, Osamu Sakurai, Toshiki Murata, Klaus Urbahns, Noriyuki Yamamoto, Satoru Yoshikawa, Masaomi Umeda, Masaomi Tajimi, Tsutomu Masuda, Takuya Shintani, Haruka Shimizu
  • Publication number: 20060154912
    Abstract: The present invention relates to isophthalic acid derivatives, to a process for their preparation and to their use for producing medicaments for the treatment and/or prophylaxis of diseases in humans and animals, in particular of cardiovascular disorders.
    Type: Application
    Filed: November 28, 2003
    Publication date: July 13, 2006
    Inventors: Michael Harter, Jens Erguden, Frank Wunder, Hanna Tinel, Johannes Kobberling, Eva-Maria Becker, Klaus Munter, Karl-Heinz Schlemmer, Raimund Kast, Peter Kolkhof, Gunter Karig, Lars Barfacker, Walter Hubsch, Joachim Schuhmacher, Susanne Zuleger, Arnel Concepcion, Haruka Shimizu