Patents by Inventor Haruo Okano

Haruo Okano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6306756
    Abstract: A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film and causing never melting to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: October 23, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Hasunuma, Sachiyo Ito, Keizo Shimamura, Hisashi Kaneko, Nobuo Hayasaka, Junsei Tsutsumi, Akihiro Kajita, Junichi Wada, Haruo Okano
  • Patent number: 6185472
    Abstract: A semiconductor device manufacturing method capable of proceeding semiconductor device manufacturing processes according to predetermined schedules or while correcting them without testpieces is provided. The method includes the steps of collecting actually observed data during at least one of plural steps, obtaining prediction data in at least one of plural steps by using an ab initio molecular dynamics process simulator or a molecular dynamics simulator, comparing and verifying the prediction data and the actually observed data sequentially at real time, and correcting and processing the plural manufacturing process factors sequentially at real time if a difference in significance is recognized between set values for the plural manufacturing process factors and the plural manufacturing process factors estimated from the actually observed data according to comparison and verification.
    Type: Grant
    Filed: December 27, 1996
    Date of Patent: February 6, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Onga, Takako Okada, Hiroshi Tomita, Kikuo Yamabe, Haruo Okano
  • Patent number: 6132551
    Abstract: The invention is embodied in an inductively coupled plasma reactor having a conductive enclosure defining a reactor chamber interior, the enclosure including a conductive layer, and an inductive antenna external of the reactor chamber interior and facing the interior through the conductive layer and being connectable to an RF power source, the conductive layer being sufficiently thin to permit an inductive field of the inductive antenna to coupled through the conductive layer into the reactor chamber interior. A wafer pedestal for supporting a semiconductive workpiece within the reactor chamber interior is connected to an RF bias power supply whereby a workpiece on the wafer support is a bias power electrode and the conductive layer is a bias power counter electrode, so that the entire reactor enclosure is a bias power counter electrode. Preferably, the bias power electrode is biased with respect to RF ground, and the conductive reactor enclosure including the conductive layer is grounded.
    Type: Grant
    Filed: September 20, 1997
    Date of Patent: October 17, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Keiji Horioka, Haruo Okano
  • Patent number: 6093243
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: July 25, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 6090701
    Abstract: A method for the production of a semiconductor device having an electrode line formed in a semiconducting substrate is disclosed which comprises preparing a semiconducting substrate having trenches and/or contact holes formed preparatorily in a region destined to form the electrode line, forming a conductive film formed mainly of at least one member selected from among Cu, Ag, and Au on the surface of the semiconducting substrate, heat-treating the superposed Cu film while supplying at least an oxidizing gas thereto thereby flowing the Cu film to fill the trenches and/or contact holes, and removing by polishing the part of the conductive film which falls outside the region of the electrode line and completing the electrode lines consequently. During the heat treatment, a reducing gas is supplied in addition to the oxidizing gas to induce a local oxidation-reduction reaction and fluidify and/or flow the conductive film and consequently accomplish the embodiment of the conductive film in the trenches.
    Type: Grant
    Filed: June 20, 1995
    Date of Patent: July 18, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Hasunuma, Sachiyo Ito, Keizo Shimamura, Hisashi Kaneko, Nobuo Hayasaka, Junsei Tsutsumi, Akihiro Kajita, Junichi Wada, Haruo Okano
  • Patent number: 6066872
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: May 23, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 5948205
    Abstract: To planarize an insulating film formed on a semiconductor substrate, a polishing slurry containing cerium oxide is used to polish the surface of the insulating film. Using the cerium oxide included slurry as a polishing agent, the insulating film is not contaminated by alkali metals during the polishing process. Furthermore, the insulating film is polished at an enhanced polishing rate.
    Type: Grant
    Filed: July 21, 1997
    Date of Patent: September 7, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masako Kodera, Hiroyuki Yano, Atsushi Shigeta, Riichirou Aoki, Hiromi Yajima, Haruo Okano
  • Patent number: 5914275
    Abstract: To planarize an insulating film formed on a semiconductor substrate, a polishing slurry containing cerium oxide is used to polish the surface of the insulating film. Using the cerium oxide included slurry as a polishing agent, the insulating film is not contaminated by alkali metals during the polishing process. Furthermore, the insulating film is polished at an enhanced polishing rate.
    Type: Grant
    Filed: July 21, 1997
    Date of Patent: June 22, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masako Kodera, Hiroyuki Yano, Atsushi Shigeta, Riichirou Aoki, Hiromi Yajima, Haruo Okano
  • Patent number: 5888338
    Abstract: The invention provides a novel magnetron plasma processing apparatus comprising the following, a vacuum chamber storing an etching object, the first electrode which is provided in the vacuum chamber and holds the etching object, the second electrode which is disposed in opposition from the first electrode, where the first and second electrodes are in parallel with each other, a gas-supply unit feeding etching gas to the vacuum chamber, a magnetic-field generating means which is disposed on the part opposite from the first electrode in opposition from the second electrode, and a power-supply unit which feeds power to either of these first and second electrodes and generates discharge between these parallel electrodes. Magnetic-field generating means is provided with a magnetic block whose both-end surfaces are provided with magnetic poles having polarity inverse from each other, and in addition, a plane recess opposite from the second electrode is provided between both-end surfaces of the magnetic block.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: March 30, 1999
    Assignees: Tokyo Electron Limited, Kabushiki Kaisha Toshiba
    Inventors: Hiromi Harada, Sinji Kubota, Hiromi Kumagai, Junichi Arami, Keiji Horioka, Isahiro Hasegawa, Haruo Okano, Katsuya Okumura, Yukimasa Yoshida
  • Patent number: 5879447
    Abstract: A single crystal and a polycrystal having an excellent crystal quality and providing a highly reliable semiconductor device are formed by solid phase growth at low temperatures. An amorphous thin film is deposited on a substrate such that an average inter-atomic distance of main constituent element of the amorphous thin film is 1.02 times or more of an average inter-atomic distance of the elements in single crystal, and crystallization energy is applied to the amorphous thin film to perform solid phase growth to thereby form a single crystal.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 9, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takako Okada, Shigeru Kambayashi, Moto Yabuki, Shinji Onga, Yoshitaka Tsunashima, Yuuichi Mikata, Haruo Okano
  • Patent number: 5775980
    Abstract: This invention provides a polishing method including the steps of forming a film to be polished on a substrate having a recessed portion in its surface so as to fill at least the recessed portion, and selectively leaving the film to be polished behind in the recessed portion by polishing the film by using a polishing agent containing polishing particles and a solvent, and having a pH of 7.5 or more. The invention also provides a polishing apparatus including a polishing agent storage vessel for storing a polishing agent, a turntable for polishing an object to be polished, a polishing agent supply pipe for supplying the polishing agent from the polishing agent storage vessel onto the turntable, a polishing object holding jig for holding the object to be polished such that the surface to be polished of the object opposes the turntable, and a polishing agent supply pipe temperature adjusting unit, connected to the polishing agent supply pipe, for adjusting the temperature of the polishing agent.
    Type: Grant
    Filed: November 4, 1996
    Date of Patent: July 7, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasutaka Sasaki, Mie Matsuo, Rempei Nakata, Junichi Wada, Nobuo Hayasaka, Hiroyuki Yano, Haruo Okano
  • Patent number: 5776557
    Abstract: A thin film forming method which comprises the steps of supporting a substrate to be treated, having a trench or an unevenness thereon, in a reaction vessel; introducing a reactive gas into the reaction vessel; activating the reactive gas to form a deposit species, the deposit species characterized by a phase diagram including a liquid phase region defined by a melting curve and an evaporation curve that intersect at a triple point; and forming a thin film containing at least a part of the deposit species on the substrate while retaining a pressure of the deposit species in the reaction vessel higher than the triple point of the phase diagram of the deposit species, and retaining a temperature of the substrate within the liquid phase region of the phase diagram of the deposit species.
    Type: Grant
    Filed: October 10, 1996
    Date of Patent: July 7, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Haruo Okano, Sadahisa Noguchi, Makoto Sekine
  • Patent number: 5733713
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method comprises the steps of forming carbon layer on a light-reflective layer or a transparent layer formed on a light-reflective layer, forming a photosensitive resin layer on the carbon layer, selectively radiating light on the photosensitive resin layer, forming a photosensitive resin pattern by developing the photosensitive resin layer selectively irradiated with the light, forming a carbon pattern by etching the carbon layer using the photosensitive pattern as a mask, and forming a light-reflective pattern or a transparent layer pattern by etching the light-reflective layer using the photosensitive resin layer or the carbon pattern as a mask. When the light-reflective layer pattern is formed, the thickness of the carbon layer is set to be less than 100 nm. When the transparent layer pattern is formed, the thickness of the carbon layer is set to be 80 nm or more.
    Type: Grant
    Filed: April 21, 1995
    Date of Patent: March 31, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Yano, Haruo Okano, Tohru Watanabe, Keiji Horioka
  • Patent number: 5731634
    Abstract: The present invention provides a method of manufacturing a semiconductor device, including the steps of forming a metal oxide film made of a metal oxide having a decrease in standard free energy smaller than a decrease in standard free energy of hydrogen oxide or of carbon oxide, on an insulating film formed on a semiconductor substrate, forming a metal oxide film pattern by subjecting a treatment to the metal oxide film, and converting said metal oxide pattern into at least one of an electrode and a wiring made of a metal which is a main component constituting the metal oxide, by reducing the metal oxide film pattern at a temperature of 80.degree. to 500.degree. C.
    Type: Grant
    Filed: June 6, 1996
    Date of Patent: March 24, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mie Matsuo, Haruo Okano, Nobuo Hayasaka, Kyoichi Suguro, Hideshi Miyajima, Jun-ichi Wada
  • Patent number: 5707487
    Abstract: According to this invention, a method of manufacturing a semiconductor device includes the steps of forming a carbon film on a surface of a substrate, forming a mask pattern on the carbon film, etching the carbon film along the mask pattern to form a carbon film pattern, and reactive ion etching the substrate along the carbon film pattern using a high density plasma produced by application of a high frequency and a magnetic field, application of a microwave, irradiation of an electron beam, application of a high frequency of not less than 27 MHz, or application of a inductive coupled high frequency.
    Type: Grant
    Filed: October 31, 1994
    Date of Patent: January 13, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaru Hori, Hiroyuki Yano, Keiji Horioka, Haruo Okano
  • Patent number: 5686151
    Abstract: Disclosed is method of forming a metal oxide film including the steps of introducing a gas containing a metal compound having at least one element selected from the group consisting of carbon and a halogen element, into a process chamber accommodating a substrate, introducing a gas containing a compound having a hydroxyl group into the process chamber, introducing a gas containing oxygen which has been converted to a plasma state, into the process chamber, and forming the metal oxide film on the substrate using the gas containing a metal compound, the gas containing a compound having a hydroxyl group, and the gas containing oxygen which has been converted to a plasma state.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: November 11, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keitaro Imai, Masahiro Kiyotoshi, Haruo Okano
  • Patent number: 5679484
    Abstract: An exposure mask having an excellent alignment accuracy between patterns, which is prepared by first forming on a light transmissive substrate a light shielding film or a semi-transparent film pattern (first pattern) somewhat larger than a desired dimension, forming thereon a semi-transparent film or a light transmissive film pattern (second pattern) so as to include all patterns of the desired dimensions made up of a light shielding part, a semi-transparent part and a light transmissive part, and then removing a projected part of the first pattern with use of the second pattern as a mask.The semi-transparent film is formed of at least two layers each of which contains a common element, thus the semi-transparent film can be made with use of the same apparatus and when patterning, etching process can be carried out with use of the same etchant.
    Type: Grant
    Filed: November 25, 1996
    Date of Patent: October 21, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Ito, Haruo Okano, Toru Watanabe, Katsuya Okumura
  • Patent number: 5660671
    Abstract: A magnetron plasma processing apparatus includes, a vacuum chamber storing an etching object, a first electrode which is provided in the vacuum chamber and holds the etching object, a second electrode which is disposed in opposition from the first electrode and parallel with the first electrode. A gas-supply unit feeding etching gas to the vacuum chamber while, a magnetic-field generating means is disposed on the part opposite from the first electrode in opposition from the second electrode, and a power-supply unit feeds power to either the first or second electrodes and generates discharge between the electrodes. The magnetic-field generating means is provided with a magnetic block whose both-end surfaces are provided with magnetic poles having polarity inverse from each other, and in addition, a plane recess opposite from the second electrode is provided between both-end surfaces of the magnetic block.
    Type: Grant
    Filed: June 28, 1994
    Date of Patent: August 26, 1997
    Assignees: Tokyo Electron Limited, Kabushiki Kaisha Toshiba
    Inventors: Hiromi Harada, Sinji Kubota, Hiromi Kumagai, Junichi Arami, Keiji Horioka, Isahiro Hasegawa, Haruo Okano, Katsuya Okumura, Yukimasa Yoshida
  • Patent number: 5660744
    Abstract: A surface processing apparatus comprises a container provided with a first electrode and a second electrode disposed opposite to the first electrode for supporting a substrate to be processed and filled with a gas at a reduced pressure, an electric field generator for generating an electric field between the first and second electrodes, and a magnetic field generator for generating a magnetic field in the vacuum container. The magnetic field generator comprises a plurality of magnet element groups arranged in a circle around the container so as to form a ring, each of the magnet element groups having an axis directed to a center of the circle and a synthetic magnetization direction and comprising one or a plurality of magnet elements having respective magnetization directions which are synthesized to be equal to the synthetic magnetization direction of the each of the magnetic element groups.
    Type: Grant
    Filed: June 19, 1995
    Date of Patent: August 26, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Sekine, Keiji Horioka, Haruo Okano, Katsuya Okumura, Isahiro Hasegawa, Masaki Narita
  • Patent number: 5661345
    Abstract: The method of producing a semiconductor device includes the steps of forming a groove having a predetermined pattern shape on the surface of a substrate; forming a metal film on the substrate while reaction with the surface of the substrate is suppressed; and agglomerating the metal film by in-situ annealing, wherein agglomeration of the metal film is started before the metal film reacts with the surface of the substrate due to annealing, while formation of a native oxide on the metal film is suppressed, and whereby the metal film is filled into the groove by annealing at a predetermined temperature for a predetermined period of time. The structure of the semiconductor device includes an insulator in which there is formed a groove portion having a predetermined pattern shape and an electrode interconnection made of a single-crystal metal which is filled in the groove portion.
    Type: Grant
    Filed: December 1, 1994
    Date of Patent: August 26, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junichi Wada, Hisashi Kaneko, Kyoichi Suguro, Nobuo Hayasaka, Haruo Okano