Abstract: An apparatus for CMP includes a wafer carrier retaining a semiconductor wafer during a polishing operation, a slurry dispenser dispensing an abrasive slurry, and a slurry temperature control device coupled to the shiny dispenser and configured to control a temperature of the abrasive slurry. The slurry temperature control device includes a heat transferring portion surrounding a portion of the slurry dispenser, and a thermos-electric (TE) chip coupled to the heat transferring portion and configured to control the temperature of the abrasive slurry.

Abstract: A wafer polishing head is provided. The wafer polishing head includes a carrier head, a plurality of piezoelectric actuators disposed on the carrier head, and a membrane disposed over the plurality of piezoelectric actuators. The plurality of piezoelectric actuators is configured to provide mechanical forces on the membrane and generate an electrical charge when receiving counterforces of the mechanical forces through the membrane. A wafer polishing system and a method for polishing a substrate using the same are also provided.

Abstract: A wafer polishing head is provided. The wafer polishing head includes a carrier head, a plurality of piezoelectric actuators disposed on the carrier head, and a membrane disposed over the plurality of piezoelectric actuators. The plurality of piezoelectric actuators is configured to provide mechanical forces on the membrane and generate an electrical charge when receiving counterforces of the mechanical forces through the membrane. A wafer polishing system and a method for polishing a substrate using the same are also provided.

Abstract: A method for polishing a semiconductor substrate includes the following operations. A semiconductor substrate is received. An abrasive slurry having a first temperature is dispensed to a polishing surface of a polishing pad. The semiconductor substrate is polished. The abrasive slurry have a second temperature is dispensed to the polishing surface of the polishing pad during the polishing of the semiconductor substrate. The second temperature is different from the first temperature.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: A wafer polishing head is provided. The wafer polishing head includes a carrier head, a plurality of piezoelectric actuators disposed on the carrier head, and a membrane disposed over the plurality of piezoelectric actuators. The plurality of piezoelectric actuators is configured to provide mechanical forces on the membrane and generate an electrical charge when receiving counterforces of the mechanical forces through the membrane. A wafer polishing system and a method for polishing a substrate using the same are also provided.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: An apparatus for CMP includes a wafer carrier retaining a semiconductor wafer during a polishing operation, a slurry dispenser dispensing an abrasive slurry, and a slurry temperature control device coupled to the shiny dispenser and configured to control a temperature of the abrasive slurry. The slurry temperature control device includes a heat transferring portion surrounding a portion of the slurry dispenser, and a thermos-electric (TE) chip coupled to the heat transferring portion and configured to control the temperature of the abrasive slurry.

Abstract: An apparatus for CMP includes a wafer carrier retaining a semiconductor wafer during a polishing operation, a slurry dispenser dispensing an abrasive slurry, and a temperature control system monitoring and controlling a temperature variation during the polishing operation. The temperature control system includes a temperature sensor detecting a temperature during the polishing operation and providing a signal corresponding to the temperature, a temperature controller coupled to the temperature sensor and receiving the signal from the temperature sensor, and a cooling device coupled to the temperature controller and providing a coolant to the apparatus for CMP.

Abstract: An apparatus for CMP includes a platen, a wafer carrier retaining a semiconductor wafer during a polishing operation, a dresser configured to recondition a polishing pad disposed on the platen during the polishing operation, and a vibration-monitoring system configured to detect vibrations during the polishing operation. The vibration-monitoring system includes a first vibration sensor configured to generate a plurality of first vibration signals. An end point is triggered to the polishing when a change between the plurality of vibration signals reaches a value.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: An apparatus for CMP includes a platen, a wafer carrier retaining a semiconductor wafer during a polishing operation, a dress configured to recondition a polishing pad disposed on the platen during the polishing operation, and a vibration-monitoring system configured to detect vibrations during the polishing operation. The vibration-monitoring system includes a first vibration sensor configured to generate a plurality of first vibration signals. An end point is triggered to the polishing when a change between the plurality of vibration signals reaches a value.

Abstract: An apparatus for CMP includes a wafer carrier retaining a semiconductor wafer during a polishing operation, a slurry dispenser dispensing an abrasive slurry, and a temperature control system monitoring and controlling a temperature variation during the polishing operation. The temperature control system includes a temperature sensor detecting a temperature during the polishing operation and providing a signal corresponding to the temperature, a temperature controller coupled to the temperature sensor and receiving the signal from the temperature sensor, and a cooling device coupled to the temperature controller and providing a coolant to the apparatus for CMP.

Abstract: A method for cleaning a brush includes inducing a static charge on a surface of a first plate, wherein the first plate comprises at least one of silicon nitride (SixNy) or silicon oxide (SiaOb), wherein a, b, x and y are integers. The method further includes rotating the brush in contact with the surface of the first plate.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: Embodiments of mechanisms for performing a chemical mechanical polishing (CMP) process are provided. A method for performing a CMP process includes polishing a wafer by using a polishing pad. The method also includes applying a cleaning liquid jet on the polishing pad to condition the polishing pad. A CMP system is also provided.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution.