Abstract: A semiconductor chip structure may include a semiconductor chip, a first insulation layer and a redistribution layer. The first insulation layer may be formed on the semiconductor chip. The first insulation layer may have at least one first groove formed at an upper surface portion of the first insulation layer. Further, the at least one first groove may have an upper width and a lower width greater than the upper width. The redistribution layer may be partially formed on the first insulation layer. The redistribution layer may have at least one first protrusion formed on a lower surface portion of the redistribution layer. The first protrusion may have an upper width and a lower width less than the upper width. The first protrusion may be inserted into the at least one first groove.

Abstract: In a memory module, a gap filler for eliminating an air gap may be formed on an end of a PCB where a tab may be formed. The gap filler may be formed on a surface of a socket receiving the memory module. A grease may be coated on the tab to provide a heat conduction path away from the memory module.

Abstract: In a memory module, a gap filler for eliminating an air gap may be formed on an end of a PCB where a tab may be formed. The gap filler may be formed on a surface of a socket receiving the memory module. A grease may be coated on the tab to provide a heat conduction path away from the memory module.

Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor device having a bonding pad and an interlayer insulating layer disposed on the semiconductor device. The interlayer insulating layer has an opening which exposes the bonding pad and has at least one cavity therein. A redistributed interconnection is disposed on the interlayer insulating layer and electrically connected to the exposed bonding pad. The redistributed interconnection is disposed over the cavity. A method of fabricating the semiconductor package is also provided.

Abstract: A semiconductor device and a method for fabricating the same are disclosed. According to some embodiments, a semiconductor device comprises a lower structure formed on a semiconductor structure. The lower structure has chip pads. The semiconductor device further comprises a passivation layer located over the chip pads. The passivation layer comprises first openings defined therein to expose at least a portion of the chip pads. The semiconductor device additionally includes at least two adjacent redistribution lines spaced apart from each other and located over the passivation layer. The at least two redistribution lines are respectively coupled to the chip pads through corresponding ones of the first openings. The semiconductor device comprises a first insulation layer located over the passivation layer. The first insulation layer includes a void extending between the at least two adjacent redistribution lines.

Abstract: A semiconductor chip structure may include a semiconductor chip, a first insulation layer and a redistribution layer. The first insulation layer may be formed on the semiconductor chip. The first insulation layer may have at least one first groove formed at an upper surface portion of the first insulation layer. Further, the at least one first groove may have an upper width and a lower width greater than the upper width. The redistribution layer may be partially formed on the first insulation layer. The redistribution layer may have at least one first protrusion formed on a lower surface portion of the redistribution layer. The first protrusion may have an upper width and a lower width less than the upper width. The first protrusion may be inserted into the at least one first groove.

Abstract: A multi-chip package comprises a double-sided circuit board having first and second surfaces. Each surface has a package area and a peripheral area. Each package area has a chip mounting area on which a chip is attached, and a bonding area with which the chip is electrically connected. The peripheral area of the first surface has a runner area on which molding compound flows, and the peripheral area of the second surface has external connection pattern with which the bonding areas are electrically connected. In particular, the circuit board has gate holes, which are co-located on each surface to result in a common hole.

Abstract: In one embodiment, a pad is formed on a substrate surface. The pad is connected with a connecting pattern. A first mask is formed on the substrate. The first mask has a first opening exposing at least a portion of the pad and a portion of the connecting pattern. A second mask is formed on the first mask, The second mask has a second opening exposing at least a portion of the pad and a portion of the connecting pattern. A boundary surface or sidewall of the first opening is not coplanar with a boundary surface or sidewall of the second opening. Therefore, stresses may be prevented from concentrating on the boundary surface of the first opening, thereby allowing dispersion of the stresses and restraining pattern cracks.

Abstract: In one embodiment, a pad is formed on a substrate surface. The pad is connected with a connecting pattern. A first mask is formed on the substrate. The first mask has a first opening exposing at least a portion of the pad and a portion of the connecting pattern. A second mask is formed on the first mask. The second mask has a second opening exposing at least a portion of the pad and a portion of the connecting pattern. A boundary surface or sidewall of the first opening is not coplanar with a boundary surface or sidewall of the second opening. Therefore, stresses may be prevented from concentrating on the boundary surface of the first opening, thereby allowing dispersion of the stresses and restraining pattern cracks.

Abstract: Example embodiments of a semiconductor chip packaging apparatus and method thereof are disclosed. The packaging apparatus may include a plating unit to perform a conductive plating process to form a conductive plating layer on external terminals of a semiconductor chip package, and a reflow unit adapted to melt the conductive plating layer. The plating unit and reflow unit may be disposed in a single line with the plating module. Thus, it is possible to effectively suppress the growth of whiskers on the plating layer of the external terminals, and to secure economical efficiency, reducing costs, and allowing mass production.

Abstract: Provided herein are multi-chip modules (MCMs) having bonding wires and fabrication methods thereof. The multi-chip module includes a substrate and a plurality of chips sequentially stacked. At least one top chip, stacked above a lowest chip, has an insulating film that covers the backside thereof. Also, each of the stacked chips has bonding pads formed on the periphery or edges of its upper surface. At least one insulator is interposed between the stacked chips. The insulator exposes the pads on the underlying chip. The pads of the respective chips are connected to a set of interconnections, which are disposed on the substrate. This configuration of stacked chips enables the overall height of the memory module to be reduced because the insulating film prevents the bonding wires from contacting the substrate of the top chips.

Abstract: Provided herein are multi-chip modules (MCMs) having bonding wires and fabrication methods thereof. The multi-chip module includes a substrate and a plurality of chips sequentially stacked. At least one top chip, stacked above a lowest chip, has an insulating film that covers the backside thereof. Also, each of the stacked chips has bonding pads formed on the periphery or edges of its upper surface. At least one insulator is interposed between the stacked chips. The insulator exposes the pads on the underlying chip. The pads of the respective chips are connected to a set of interconnections, which are disposed on the substrate. This configuration of stacked chips enables the overall height of the memory module to be reduced because the insulating film prevents the bonding wires from contacting the substrate of the top chips.

Abstract: In a memory module, a gap filler for eliminating an air gap may be formed on an end of a PCB where a tab may be formed. The gap filler may be formed on a surface of a socket receiving the memory module. A grease may be coated on the tab to provide a heat conduction path away from the memory module.

Abstract: In one embodiment, a pad is formed on a substrate surface. The pad is connected with a connecting pattern. A first mask is formed on the substrate. The first mask has a first opening exposing at least a portion of the pad and a portion of the connecting pattern. A second mask is formed on the first mask. The second mask has a second opening exposing at least a portion of the pad and a portion of the connecting pattern. A boundary surface or sidewall of the first opening is not coplanar with a boundary surface or sidewall of the second opening. Therefore, stresses may be prevented from concentrating on the boundary surface of the first opening, thereby allowing dispersion of the stresses and restraining pattern cracks.

Abstract: Provided herein are multi-chip modules (MCMs) having bonding wires and fabrication methods thereof. The multi-chip module includes a substrate and a plurality of chips sequentially stacked. At least one top chip, stacked above a lowest chip, has an insulating film that covers the backside thereof. Also, each of the stacked chips has bonding pads formed on the periphery or edges of its upper surface. At least one insulator is interposed between the stacked chips. The insulator exposes the pads on the underlying chip. The pads of the respective chips are connected to a set of interconnections, which are disposed on the substrate. This configuration of stacked chips enables the overall height of the memory module to be reduced because the insulating film prevents the bonding wires from contacting the substrate of the top chips.

Abstract: A first semiconductor chip is attached to a first side of a printed circuit board, and a second semiconductor chip is attached to a second side of the printed circuit board opposite the first side of the printed circuit board. A mold is then used to form a first mold cavity which contains the first semiconductor chip over the first side of the printed circuit board, and to form a second mold cavity which contains the second semiconductor chip over the second side of the printed circuit board. The first and second mold cavities are simultaneously filled with a fill material via a mold inlet, where the mold inlet is at least partially defined through an aperture in the printed circuit board from the first side to the second side.

Abstract: Provided are a molding method for encapsulating in a substantially simultaneous manner wafer level packages (WLPs) arranged on opposite sides of a PCB module and a mold suitable for practicing the molding method. A PCB module is secured between an upper mold and a lower mold that cooperate to form a single mold. The upper mold includes an upper cavity for receiving an upper WLP and an upper gate through which an epoxy molding compound (EMC) may be forced into the upper cavity. The lower mold includes a lower cavity for receiving a lower WLP and a lower gate through which EMC may be forced into the lower cavity. The EMC may enter the gates through a single inlet formed between upper and lower inlet forming blocks, thereby encapsulating both the upper and lower sides of the PCB module substantially simultaneously, thereby improving productivity.

Abstract: A die package and a die packaging technique, and more particularly a double-sided circuit board mounting technique and a multi-chip package including the circuit board. The multi-chip package comprises a circuit board having the first surface and the second surface. The first surface has a package area and the peripheral area. The package area comprises the chip mounting area on which the die is attached and bonding area with which the die is electrically connected. Additionally, the peripheral area comprises a runner area on which molding compound flows. In the boundary area between the package area and the peripheral area, a gate hole is connected with the runner area. The second surface has a package area and perimeter. The package area comprises the chip mounting area on which the die is attached and the bonding area with which the die is electrically connected. Additionally, the peripheral area comprises the external connection patterns with which the die is electrically connected.

Abstract: A semiconductor package and a manufacturing method prevent electrical shorts that otherwise result from bonding wires contacting the edge of a semiconductor chip. An insulating region at the edge of a semiconductor chip prevents the shorts. One method for forming the insulating region leaves a polyimide layer on the scribe area of a wafer and cuts through the polyimide layer. To avoid chipping, the cutting uses a fine grit blade and a slow cutting rate. An alternative process removes the polyimide from the scribe area and forms the insulating region on the edge of the semiconductor chip. A potting method can deposit the insulating region on a semiconductor chip after cutting a wafer and after attaching a separated chip to a substrate. Alternatively, plotting or printing can apply insulating material on the wafer. A cutting process then cuts through the insulating material and the wafer and leaves insulating regions on each separated chip.

Abstract: An embodiment of the present invention provides a pickup tool in accordance with the present invention includes multiple contact parts, which contact a passivation layer of a semiconductor chip so that the contact parts are far from chip pads and fuses when holding the semiconductor chip. Furthermore, a die bonding apparatus has one or two pickup tools, an aligning stage, and a bond stage or a bond head.