Abstract: Provided is a technique for forming an indium field implant at the bottom of an STI trench to strengthen the p-well under field oxide, but to not weaken the n-well under the field oxide. The diffusivity of indium is an order of magnitude smaller than that of boron and the activation level of indium is high enough for well dopings. Thus, the implanted indium is able to keep the concentration of p-dopant at the p-n well junction under the field isolation and the oxide/silicon interface high, even with boron depletion, so that punchthrough is avoided.

Abstract: A method of forming junctions in a semiconductor substrate, where a gate dielectric layer is grown on the semiconductor substrate, a gate electrode layer is deposited on the gate dielectric layer, and a sacrificial layer is formed on the gate electrode layer. The sacrificial layer is patterned with a material to cover portions of the sacrificial layer and expose portions of the sacrificial layer. The exposed portions of the sacrificial layer are etched to remove the exposed portions of the sacrificial layer and expose portions of the gate electrode layer. The exposed portions of the gate electrode layer are etched to expose portions of the gate dielectric layer and form a gate electrode having exposed vertical faces. The sacrificial layer and the exposed portions of the gate dielectric layer are impregnated with a first species that inhibits diffusion of oxygen through the sacrificial layer and the exposed portions of the gate dielectric layer.

Abstract: A method for fabricating an SRAM device having a standard well tub, where an additional well tub is deposited within the standard well tub. In this manner, the dopant concentration is increased in the well area of the SRAM device, which increases both the isolation punchthrough tolerance and the SER immunity of the device. The additional well tub is deposited to a depth that is shallower than the standard well tub. The additional well tub is deposited using an ion implantation process using the same mask set as that used for the threshold voltage adjustment deposition. Thus, no additional mask layer is required to deposit the additional well tub, and the all of the expenses normally associated with an additional mask layer are avoided.

Abstract: An integrated circuit structures such as an SRAM construction wherein the soft error rate is reduced comprises an integrated circuit structure formed in a semiconductor substrate, wherein at least one N channel transistor is built in a P well adjacent to one or more deep N wells connected to the high voltage supply and the deep N wells extend from the surface of the substrate down into the substrate to a depth at least equal to that depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell. For a 0.25 &mgr;m SRAM design having one or more N wells of a conventional depth not exceeding about 0.5 &mgr;m, the depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell is from 1 to 3 &mgr;m. The deep N well of the 0.25 &mgr;m SRAM design, therefore, extends down from the substrate surface a distance of at least about 1 &mgr;m, and preferably at least about 2 &mgr;m.

Abstract: A method for fabricating an SRAM device having a standard well tub, where an additional well tub is deposited within the standard well tub. In this manner, the dopant concentration is increased in the well area of the SRAM device, which increases both the isolation punchthrough tolerance and the SER immunity of the device. The additional well tub is deposited to a depth that is shallower than the standard well tub. The additional well tub is deposited using an ion implantation process using the same mask set as that used for the threshold voltage adjustment deposition. Thus, no additional mask layer is required to deposit the additional well tub, and the all of the expenses normally associated with an additional mask layer are avoided.

Abstract: A process for inhibiting the passage of dopant from a gate electrode into a thin gate oxide comprises nitridation of the upper surface of the thin gate oxide, prior to formation of the gate electrode over the gate oxide, to thereby form a barrier of nitrogen atoms in the upper surface region of the gate oxide adjacent the interface between the gate oxide and the gate electrode to inhibit passage of dopant atoms from the gate electrode into the thin gate oxide during annealing of the structure. In one embodiment, a selective portion of silicon oxide on a silicon substrate may be etched to thin the oxide to the desired thickness using a nitrogen plasma with a bias applied to the silicon substrate. Nitridation of the surface of the etched silicon oxide is then carried out in the same apparatus by removing the bias from the silicon substrate.

Abstract: A method for fabricating a semiconducting device on a substrate, where the improvement includes forming a strained silicon carbide channel layer on the substrate. A silicon layer is formed on top of the strained silicon carbide channel layer. A gate insulation layer is formed on top of the silicon layer and strained silicon carbide channel layer, at a temperature that does not exceed about eight hundred centigrade. A gate electrode is formed on top of the gate insulation layer, and the gate electrode is patterned. A low dose drain dopant is impregnated into the substrate, and activated with a first laser anneal. A source drain dopant is impregnated into the substrate, and activated with a second laser anneal. After the step of activating the low dose drain dopant with the first laser anneal, an insulating layer is formed around the gate electrode, at a temperature that does not exceed about eight hundred centigrade, and a spacer is formed around the gate electrode.

Abstract: Provided is a technique for forming an indium field implant at the bottom of an STI trench to strengthen the p-well under field oxide, but to not weaken the n-well under the field oxide. The diffusivity of indium is an order of magnitude smaller than that of boron and the activation level of indium is high enough for well dopings. Thus, the implanted indium is able to keep the concentration of p-dopant at the p-n well junction under the field isolation and the oxide/silicon interface high, even with boron depletion, so that punchthrough is avoided.

Abstract: A process is described for using a silicon layer as an implant and out-diffusion layer, for forming defect-free source/drain regions in a semiconductor substrate, and also for subsequent formation of silicon nitride spacers. A nitrogen-containing dopant barrier layer is first formed over a single crystal semiconductor substrate by nitridating either a previously formed gate oxide layer, or a silicon layer formed over the gate oxide layer, to form a barrier layer comprising either a silicon, oxygen, and nitrogen compound or a compound of silicon and nitrogen. The nitridating may be carried out using a nitrogen plasma followed by an anneal. A polysilicon gate electrode is then formed over this barrier layer, and the exposed portions of the barrier layer remaining are removed. An amorphous silicon layer of predetermined thickness is then formed over the substrate and polysilicon gate electrode.

Abstract: Provided is a technique for fabrication of a nitrided gate oxide and shallow trench isolation (STI) oxide liner in a semiconductor depletion into STI oxide and the RNCE in CMOS devices by introducing nitrogen to the STI edges of the p-well. This technique improves isolation performance and is also effective to harden the oxide to reduce boron penetration. Nitridization of the STI liner may be conducted on its own or in combination with gate oxide nitridization, both with beneficial effect with regard to the RNCE. The nitridization may also be focussed on the channel region of the gate oxide in particular in order to mitigate RSCE.

Abstract: An isolation trench in a silicon semiconductor substrate is provided with a barrier region containing nitrogen atoms formed in the trench, contiguous with the silicon semiconductor substrate surfaces of the trench. The novel isolation trench structure of the invention is formed by forming an isolation trench in a silicon semiconductor substrate; forming in the isolation trench a barrier region by treating the trench structure with nitrogen atoms from a nitrogen plasma; and then forming a silicon oxide layer over the barrier region in the trench to confine the nitrogen atoms in the barrier region. In a preferred embodiment, a silicon oxide liner is first formed over the silicon semiconductor substrate surfaces of the trench, and then the trench structure is treated with nitrogen atoms from a nitrogen plasma to form, on the silicon semiconductor substrate surfaces of the trench, a barrier layer which contains silicon atoms, oxygen atoms, and nitrogen atoms.

Abstract: A multiple well formation is provided in a CMOS region of a semiconductor substrate to provide enhanced latchup protection for one or more CMOS transistors formed in the wells. The structure comprises an N well extending from the substrate surface down into the substrate, a buried P well formed in the substrate beneath the N well, a second P well extending from the substrate surface down into the substrate, and an isolation region formed in the substrate between the N well and the second P well. The buried P well may extend beneath both the N well and the second P well in the substrate. In a preferred embodiment of the invention, the N well and the second P well are each implanted in the substrate at an energy level sufficient to provide a dopant concentration peak in the substrate below the depth of the isolation region to provide punch through protection and to provide a channel stop beneath the isolation region by proving a P-N junction between the N well and P well beneath the isolation region.

Abstract: A method of forming a supersaturated layer on a semiconductor device, where an initial phase layer is deposited on the semiconductor device. The initial phase layer has a solid phase dopant saturation level and a liquid phase dopant saturation level, where the liquid phase dopant saturation level is greater than the solid phase dopant saturation level. A concentration of a dopant is impregnated within the initial phase layers, where the concentration of the dopant is greater than the solid phase dopant saturation level and no more than about the liquid phase dopant saturation level. The initial phase layer is annealed, without appreciably heating the semiconductor device, using an amount of energy that is high enough to liquefy the initial phase layer over a melt duration. This dissolves the dopant in the liquefied initial phase layer. The amount of energy is low enough to not appreciably gasify or ablate the initial phase layer.