Patents by Inventor Henning Sirringhaus

Henning Sirringhaus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120112178
    Abstract: An optoelectronic device comprises electon donor D and acceptor A semiconducting species and an intervening co-oligomeric or copolymeric species provided to alter the energy transfer characteristics of excitons to or from the interface between the said electron acceptor and donor species. The intervening species may be of the form Am-Xn-Do, where m, n and o are each 0 or a positive integer and at least two of A, X and D are present.
    Type: Application
    Filed: July 12, 2010
    Publication date: May 10, 2012
    Applicant: CAMBRIDGE ENTERPRISE LIMITED
    Inventors: Richard Friend, Wilheim Huck, Guoli Tu, Henning Sirringhaus, Neil Greenham, Martin Heeney
  • Patent number: 8174634
    Abstract: A method is provided for fabricating a multilayer electronic device on a flexible substrate including at least a first and a second patterned layer, wherein the first patterned layer is defined with a linewidth that is smaller than the linewidth of the second patterned layer, and the second patterned layer is defined by a patterning technique which is capable of correcting for local distortions of the pattern of said first layer on top of the flexible substrate and wherein the first patterned layer is laid-out in such a way that the geometric overlap between a portion of the second layer and a portion of the first layer is insensitive against small variations of the position of the second patterned layer.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: May 8, 2012
    Assignee: Plastic Logic Limited
    Inventors: Henning Sirringhaus, Seamus Burns
  • Patent number: 8153512
    Abstract: A method of forming a patterned layer, including the steps of: (i) depositing via a liquid medium a first material onto a substrate to form a first body on said substrate; (ii) depositing via a liquid medium a second material onto said substrate to form a second body, wherein said first body is used to control said deposition of said second material so as to form a patterned structure including said first and second bodies; and (iii) using said patterned structure to control the removal of selected portions of a layer of material in a dry etching process or in a wet etching process using a bath of etchant.
    Type: Grant
    Filed: December 5, 2005
    Date of Patent: April 10, 2012
    Assignee: Plastics Logic Limited
    Inventor: Henning Sirringhaus
  • Publication number: 20120037901
    Abstract: The present invention provides highly-stable oxide semiconductors which make it possible to provide devices having an excellent stability. The oxide semiconductor according to the present invention is an amorphous oxide semiconductor including at least one of indium (In), zinc (Zn), and Tin (Sn) and at least one of an alkaline metal or an alkaline earth metal having an ionic radius greater than that of gallium (Ga), and oxygen.
    Type: Application
    Filed: April 24, 2009
    Publication date: February 16, 2012
    Applicants: CAMBRIDGE ENTERPRISE LTD., PANASONIC CORPORATION
    Inventors: Kiyotaka Mori, Henning Sirringhaus, Kulbinder Kumar Banger, Rebecca Lorenz Peterson
  • Patent number: 8080152
    Abstract: An electrochemical sensor and method of its production comprising a microfluidic channel and an electronic sensing device on a first substrate, and a second substrate bonded to the first substrate so as to close the microfluidic channel, wherein a functional part of the electronic sensing device is exposed at the surface of the microfluidic channel and wherein the microfluidic channel is formed by embossing. In one embodiment the electronic device is a vertical-channel field-effect transistor.
    Type: Grant
    Filed: March 17, 2004
    Date of Patent: December 20, 2011
    Assignee: Cambridge Enterprise Ltd.
    Inventor: Henning Sirringhaus
  • Patent number: 8071180
    Abstract: A method for forming an electronic device having a semiconducting active layer comprising a polymer, the method comprising aligning the chains of the polymer parallel to each other by bringing the polymer into a liquid-crystalline phase.
    Type: Grant
    Filed: January 16, 2004
    Date of Patent: December 6, 2011
    Assignee: Cambridge University Technical Services Limited
    Inventors: Henning Sirringhaus, Richard Henry Friend, Richard John Wilson
  • Publication number: 20110232954
    Abstract: The present invention provides a method of patterning an electronic or photonic material on a substrate comprising: forming a film of said electronic or photonic material on said substrate; and using an adhesive to selectively remove regions of said electronic or photonic material from said film, thereby leaving on said substrate said patterned electronic or photonic material.
    Type: Application
    Filed: October 29, 2009
    Publication date: September 29, 2011
    Inventors: Henning Sirringhaus, Jui-Fen Chang
  • Publication number: 20110229073
    Abstract: The present invention relates integrated optoelectronic devices comprising light emitting field-effect transistors. We describe an optoelectronic device comprising a light-emitting field effect transistor (LFET) with an organic semiconductor active layer and a waveguide integrated within the channel of the light-emitting field effect transistor, wherein said waveguide comprises a material which has a higher refractive index than said organic semiconductor. We also describe a light-emitting organic field transistor integrated with a ridge or rib waveguide incorporated within the channel of the LFET; and a similar light-emitting organic field effect transistor in which the waveguide incorporates an optical feedback mechanism.
    Type: Application
    Filed: November 26, 2009
    Publication date: September 22, 2011
    Inventors: Henning Sirringhaus, Michael C. Gwinner, Harald Geissen, Heinz Schweizer
  • Publication number: 20110207300
    Abstract: A method for forming an electronic device having a multilayer structure, comprising: embossing a surface of a substrate so as to depress first and second regions of the substrate relative to at least a third region of the substrate; depositing conductive or semiconductive material from solution onto the first and second regions of the substrate so as to form a first electrode on the first region and a second electrode on the second region, wherein the electrodes are electrically insulated from each other by the third region.
    Type: Application
    Filed: March 25, 2011
    Publication date: August 25, 2011
    Applicant: PLASTIC LOGIC LIMITED
    Inventors: Thomas Meredith BROWN, Henning SIRRINGHAUS, John Devin MACKENZIE
  • Publication number: 20110101344
    Abstract: A semiconductor device which comprises a channel layer formed from a semiconductor channel component material in the form of crystalline micro particles, micro rods, crystalline nano particles, or nano rods, and doped with a semiconductor dopant.
    Type: Application
    Filed: January 7, 2011
    Publication date: May 5, 2011
    Applicants: PANASONIC CORPORATION, CAMBRIDGE ENTERPRISE LTD.
    Inventors: Kiyotaka MORI, Henning SIRRINGHAUS
  • Patent number: 7935565
    Abstract: A method for forming an electronic device having a multilayer structure, comprising: embossing a surface of a substrate so as to depress first and second regions of the substrate relative to at least a third region of the substrate; depositing conductive or semiconductive material from solution onto the first and second regions of the substrate so as to form a first electrode on the first region and a second electrode on the second region, wherein the electrodes are electrically insulated from each other by the third region.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: May 3, 2011
    Assignee: Plastic Logic Limited
    Inventors: Thomas Meredith Brown, Henning Sirringhaus, John Devin Mackenzie
  • Patent number: 7884355
    Abstract: A transistor including a semiconductive layer; and a gate dielectric layer comprising an insulating polymer, characterised in that the insulating polymer is crosslinked and comprises one or more units having a low cohesive-energy-density and one or more crosslinking groups and the insulating polymer includes substantially no residual —OH leaving groups.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: February 8, 2011
    Assignee: Cambridge Enterprise Ltd
    Inventors: Lay-Lay Chua, Peter Kian-Hoon Ho, Henning Sirringhaus, Richard Henry Friend
  • Publication number: 20110008929
    Abstract: A method for forming an electronic device having a semiconducting active layer comprising a polymer, the method comprising aligning the chains of the polymer parallel to each other by bringing the polymer into a liquid-crystalline phase.
    Type: Application
    Filed: September 22, 2010
    Publication date: January 13, 2011
    Applicant: CAMBRIDGE UNIVERSITY TECHNICAL SERVICES LIMITED
    Inventors: Henning SIRRINGHAUS, Richard Henry FRIEND, Richard John WILSON
  • Publication number: 20100264403
    Abstract: A method for forming an electronic switching device on a substrate, wherein the method comprises depositing the active semiconducting layer of the electronic switching device onto the substrate from a liquid dispersion of ligand-modified colloidal nanorods, and subsequently immersing the substrate into a growth solution to increase the diameter and/or length of the nanorods on the substrate, and wherein the as-deposited nanorods are aligned such that their long-axis is aligned preferentially in the plane of current flow in the electronic switching device.
    Type: Application
    Filed: August 9, 2006
    Publication date: October 21, 2010
    Inventors: Henning Sirringhaus, Baoquan Sun
  • Patent number: 7763501
    Abstract: A method for forming an electronic device, comprising: forming a first conductive or semiconductive layer; forming a sequence of at least on insulating layer and at least one semiconducting layer over the first conductive or semiconductive layer; locally depositing solvents at a localized region of the insulating layer so as to dissolve the sequence of insulating and semiconducting layers in the region to leave a void extending through the sequence of layer; and depositing conductive or semiconductive material in the void.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: July 27, 2010
    Assignee: Plastic Logic Limited
    Inventors: Henning Sirringhaus, Richard Henry Friend, Takeo Kawase
  • Publication number: 20100155708
    Abstract: A technique for isolating electrodes on different layers of a multilayer electronic device across an array containing more than 100000 devices on a plastic substrate. The technique comprises depositing a bilayer of a first dielectric layer (6) of a solution-processible polymer dielectric and a layer of parylene (9) to isolate layers of conductor or semiconductor on different levels of the device. The density of defects located in the active area of one of the multilayer electronic devices is typically more than 1 in 100000.
    Type: Application
    Filed: May 12, 2008
    Publication date: June 24, 2010
    Applicant: PLASTIC LOGIC LIMITED
    Inventors: Timothy Von Werne, Catherine Mary Ramsdale, Henning Sirringhaus
  • Patent number: 7718549
    Abstract: A method of making a transistor having first and second electrodes, a semiconductive layer, and a dielectric layer; said semiconductive layer comprising a semiconductive polymer and said dielectric layer comprising an insulating polymer; characterised in that said method comprises the steps of: (i) depositing on the first electrode a layer of a solution containing material for forming the semiconductive layer and material for forming the dielectric layer; and (ii) optionally curing the layer deposited in step (i); wherein, in step (i), the solvent drying time, the temperature of the first electrode and the weight ratio, of (material for forming the dielectric layer): (material for forming the semiconductive layer) in the solution are selected so that the material for forming the semiconductive layer and the material for forming the dielectric layer phase separate by self-organisation to form an interface between the material for forming the semiconductive layer and the material for forming the dielectric l
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: May 18, 2010
    Assignee: Cambridge University Technical Services Limited
    Inventors: Lay-lay Chua, Peter Kian-Hoon Ho, Henning Sirringhaus, Richard Henry Friend
  • Patent number: 7709306
    Abstract: A method for forming an electronic device including at least one electrically conductive and one semiconductive material deposited from solution, the method comprising: forming on the substrate a confinement structure consisting of a least a first zone and a second zone, depositing the electrically conductive material on the substrate, wherein the electrically conductive material is absent from both the first and second zone, and subsequently depositing the electrically semiconductive material from solution, wherein the semiconductive material is absent from the first zone, but not from the second zone.
    Type: Grant
    Filed: January 19, 2004
    Date of Patent: May 4, 2010
    Assignee: Plastic Logic Limited
    Inventors: Henning Sirringhaus, Catherine Ramsdale
  • Patent number: 7696090
    Abstract: A rectifying diode comprising a semiconducting layer, a first electrode, and a second electrode, wherein the width of the region of closest contact between the two electrodes is on the order of the thickness of the semiconducting layer.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: April 13, 2010
    Assignee: Plastic Logic Limited
    Inventors: Paul A. Cain, Henning Sirringhaus, Anoop Menon, Catherine Ramsdale, Tim Von Werne
  • Publication number: 20100051916
    Abstract: A method for forming an organic or partly organic switching device, comprising: depositing layers of conducting, semiconducting and/or insulating layers by solution processing and direct printing; defining microgrooves in the multilayer structure by solid state embossing; and forming a switching device inside the microgroove.
    Type: Application
    Filed: June 30, 2009
    Publication date: March 4, 2010
    Inventors: Henning SIRRINGHAUS, Richard Henry FRIEND, Natalie STUTZMANN, Paul SMITH