Abstract: A method of making a transistor having first and second electrodes, a semiconductive layer, and a dielectric layer; said semiconductive layer comprising a semiconductive polymer and said dielectric layer comprising an insulating polymer; characterised in that said method comprises the steps of: (i) depositing on the first electrode a layer of a solution containing material for forming the semiconductive layer and material for forming the dielectric layer; and (ii) optionally curing the layer deposited in step (i); wherein, in step (i), the solvent drying time, the temperature of the first electrode and the weight ratio, of (material for forming the dielectric layer): (material for forming the semiconductive layer) in the solution are selected so that the material for forming the semiconductive layer and the material for forming the dielectric layer phase separate by self-organisation to form an interface between the material for forming the semiconductive layer and the material for forming the dielectric laye

Abstract: An electronic device including at least first and second transistors integrated together on a substrate and each including an organic semiconductor region, wherein the first and second transistors are either both n-type or both p-type but wherein one of the first and second transistors is a normally-ON transistor and the other of the first and second transistors is a normally-OFF transistor.

Abstract: A method for forming an integrated circuit including at least two interconnected electronic switching devices, the method comprising forming at least part of the electronic switching devices by ink-jet printing.

Abstract: An electronic switching device comprising a source electrode, a drain electrode, an insulating layer in the region between source and drain electrode, a semiconducting layer in contact with both the source and the drain electrode, and in contact with said insulating layer, wherein the smallest distance between said source and drain electrodes is less than 1 ?m, and wherein the shape of the insulating layer is such that the path of smallest distance between the source-and drain electrodes intersects through a region of said insulating layer, so as to reduce the OFF current of the electronic switching device.

Abstract: A method of producing a metal element of an electronic device on a substrate, including the steps of: forming a mixture of a material comprising metal atoms with a liquid, depositing the material from the liquid mixture onto a substrate, and then irradiating at least part of the deposited material with light to increase the electrical conductivity of the deposited material.

Abstract: A transistor including a semiconductive layer; and a gate dielectric layer comprising an insulating polymer, characterised in that the insulating polymer is crosslinked and comprises one or more units having a low cohesive-energy-density and one or more crosslinking groups and the insulating polymer includes substantially no residual —OH leaving groups.

Abstract: A method for forming an electronic device, comprising: forming a first conductive or semiconductive layer; forming a sequence of at least on insulating layer and at least one semiconducting layer over the first conductive or semiconductive layer; locally depositing solvents at a localized region of the insulating layer so as to dissolve the sequence of insulating and semiconducting layers in the region to leave a void extending through the sequence of layer; and depositing conductive or semiconductive material in the void.

Abstract: An electrochemical sensor and method of its production comprising a microfluidic channel and an electronic sensing device on a first substrate, and a second substrate bonded to the first substrate so as to close the microfluidic channel, wherein a functional part of the electronic sensing device is exposed at the surface of the microfluidic channel and wherein the microfluidic channel is formed by embossing. In one embodiment the electronic device is a vertical-channel field-effect transistor.

Abstract: A device architecture for an active matrix display pixel comprising source addressing lines and TFT drain electrode formed on a first metal level of the device, the pixel electrode formed on a second, separate metal level, and the TFT gate electrode and gate addressing lines on a third metal level separated from both the first level and the second level by at least one dielectric layer, wherein the pixel electrode on the second level is electrically connected to the drain electrode on the first level through a via-hole connection and a pixel capacitor is formed by overlap of part of the pixel electrode on the second level with a portion of the gate addressing line of a neighbouring line of pixels on the third level. The device is formed preferably using print based methods.

Abstract: A method for forming an electronic device on a substrate, the device including a first electrically conductive region, a second electrically conductive region spaced from the first electrically conductive region and a region of an semiconductor material between the first and second electrically conductive regions and in contact with the first electrically conductive region, the method comprising doping an interfacial zone comprising least part of the periphery of the semiconductor material at the interface between the semiconductor material and the first electrically conductive region by means of a dopant contained in the first conductive material and capable of doping the semiconducting material so as to thereby enhance the conductivity of the interfacial zone.

Abstract: A method for forming an electronic device, comprising: forming a first conductive or semiconductive layer; forming a sequence of at least on insulating layer and at least one semiconducting layer over the first conductive or semiconductive layer; locally depositing solvents at a localised region of the insulating layer so as to dissolve the sequence of insulating and semiconducting layers in the region to leave a void extending through the sequence of layer; and depositing conductive or semiconductive material in the void.

Abstract: A method for forming an electronic device including at least one electrically conductive and one semiconductive material deposited from solution, the method comprising: forming on the substrate a confinement structure consisting of a least a first zone and a second zone, depositing the electrically conductive material on the substrate, wherein the electrically conductive material is absent from both the first and second zone, and subsequently depositing the electrically semiconductive material from solution, wherein the semiconductive material is absent from the first zone, but not from the second zone.

Abstract: A method for forming an electronic device having a multilayer structure, comprising: embossing a surface of a substrate so as to depress first and second regions of the substrate relative to at least a third region of the substrate; depositing conductive or semiconductive material from solution onto the first and second regions of the substrate so as to form a first electrode on the first region and a second electrode on the second region, wherein the electrodes are electrically insulated from each other by the third region.

Abstract: A new class of organic-inorganic materials for thin film semiconducting devices that exhibit good stability in air and water, as well as a new purification technique for thin film semiconducting devices that contain impurities, such as ionic species.

Abstract: A method for forming an electronic device in a multilayer structure comprising the steps of: defining a topographic profile in a laterally extending first layer; depositing at least one non-planarizing layer on top of the first layer such that the topographic profile of the surface of the or each non-planarizing layer conforms to that of the laterally extending first layer onto the top-most non-planarizing layer, such that the lateral location of the additional layer is defined by the shape of the topographic profile of the non-planarizing layer, and whereby the additional layer is laterally aligned with the topographic profile in the first layer.

Abstract: A method for forming a transistor, comprising: depositing a first material from solution in a first solvent to form a first layer of the transistor; and subsequently whilst the first material remains soluble in the first solvent, forming a second layer of the transistor by depositing over the first material a second material from /solution in a second solvent in which the first material is substantially insoluble.

Abstract: A method for forming an organic or partly organic switching device, comprising: depositing layers of conducing, semiconducting and/or insulating layers by solution processing and direct printing; defining high-resolution patterns of electroactive polymers by self-aligned formation of a surface energy barrier around a first pattern that repels the solution of a second material.

Abstract: A method for forming a transistor, comprising: depositing a first material from solution in a first solvent to form a first layer of the transistor, and subsequently whilst the first material remains soluble in the first solvent, forming a second layer of the transistor by depositing over the first material a second material from solution in a second solvent in which the first material is substantially insoluble.

Abstract: A method for forming an organic or partly organic switching device, comprising depositing layers of conducting, semiconducting and/or insulating layers by solution processing and direct printing; defining microgrooves in the multilayer structure by solid state embossing; and forming a switching device inside the microgroove.

Abstract: A field effect transistor is provided which comprises a gate electrode, a source electrode, a drain electrode, at least one organic semiconducting layer, and a hole transport layer for transferring holes from said source and drain electrodes to said organic semiconducting layer, wherein said hole transport layer comprises a layered metal chalcogenide. Processes for depositing a thin layer of a layered metal dichalcogenide on a substrate and for producing top gate structures on a layered metal chalcogenide layer in the manufacture of field effect transistors according to the invention are also provided.