Abstract: Method for performing an erase program operation. Various methods include: erasing a block of cells by: applying a program pulse to a block of memory elements in the three-dimensional memory that programs the block of memory elements to a level below an erase verify level, where the three-dimensional memory comprises memory elements stacked vertically; performing a verify step to verify voltage levels of a group of memory elements; determining that a memory element of the group is outside of a threshold window defined between the erase verify level and a compact erase threshold amount; and applying a second program pulse to the memory element. Where erasing the block of memory elements creates an erased block, where a width of the voltage distribution of the erased memory elements in the erased block is the same as or below a width of a voltage distribution associated with programmed memory elements.

Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.

Abstract: Techniques are described for reprogramming memory cells to tighten threshold voltage distributions and improve data retention. In one aspect, the memory cells of a word line WLn are reprogrammed after programming of memory cells of an adjacent, later-programmed word line WLn+1. The reprogramming can be limited to lower state memory cells of WLn which are adjacent to lower state memory cells of WL+1. A program pulse magnitude used in the reprogramming can be tailored to the data states of the WLn memory cell and the adjacent, WLn+1 memory cell. In some cases, the program pulse magnitudes can be grouped to reduce the implementation complexity and time. The reprogramming can occur after an initial program operation has completed, during an idle time of a control circuit.

Abstract: Apparatuses and techniques are described for pre-charging NAND string channels in a pre-charge phase of a program operation. In one aspect, a hole-type pre-charge process is used at the source end of a NAND string, where a bottom of the NAND string is connected to a p-well of a substrate. By applying a positive voltage to the p-well and a lower voltage, such as 0 V or a negative voltage, to the source-side select gate transistors and the memory cells, the holes from the p-well are injected into the channel In another approach, the hole-type pre-charge process and an electron-type pre-charge process are used sequentially in separate time periods. In another approach, the hole-type pre-charge process is used at the source end of a NAND string while the electron-type pre-charge process is used at the drain end of the NAND string.

Abstract: Techniques are described for reducing an injection type of program disturb in a memory device during the pre-charge phase of a program loop. In one approach, a pre-charge voltage on the selected word line and drain side word lines is adjusted based on a risk of the injection type of program disturb. Risk factors such as temperature, WLn position, Vpgm and the selected sub-block, can be used to set the pre-charge voltage to be lower when the risk is higher. In another approach, the pre-charge voltage on the source side word lines is adjusted to reduce a channel gradient and/or the amount of time in which the injection type of program disturb occurs.

Abstract: Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.

Abstract: Techniques are described for reducing an injection type of program disturb in a memory device during the pre-charge phase of a program loop. In one approach, a pre-charge voltage on the selected word line and drain side word lines is adjusted based on a risk of the injection type of program disturb. Risk factors such as temperature, WLn position, Vpgm and the selected sub-block, can be used to set the pre-charge voltage to be lower when the risk is higher. In another approach, the pre-charge voltage on the source side word lines is adjusted to reduce a channel gradient and/or the amount of time in which the injection type of program disturb occurs.

Abstract: Techniques are provided for predictively programming of non-volatile memory, which may reduce the number of verify operations. In one aspect, a programming circuit is configured to program memory cells to a verify low voltage and to program a set of the memory cells to target states. The set comprises memory cells having a threshold voltage between the verify low voltage and a verify high voltage. To program the set of the memory cells to the target states, the programming circuit is configured to apply two or more program pulses to memory cells in the set without verifying whether the memory cells have reached their respective target states, including: apply a first and second program enable voltages to the bit lines associated with the memory cells having different strengths.

Abstract: Techniques are provided for predictively programming of non-volatile memory, which may reduce the number of verify operations. In one aspect, a programming circuit is configured to program memory cells to a verify low voltage and to program a set of the memory cells to target states. The set comprises memory cells having a threshold voltage between the verify low voltage and a verify high voltage. To program the set of the memory cells to the target states, the programming circuit is configured to apply two or more program pulses to memory cells in the set without verifying whether the memory cells have reached their respective target states, including: apply a first and second program enable voltages to the bit lines associated with the memory cells having different strengths.

Abstract: Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.

Abstract: Storage device programming methods, systems and devices are described. A method may generate a mapping of data based on a set of data, the mapping of data including a first mapped data and a second mapped data. The method may include performing a first programming operation to write, in a first mode, the first mapped data to the memory device. The method may include storing the second mapped data to a cache. The method may include generating a second set of data, based on an inverse mapping of the mapping of data including the second mapped data from the cache and the first mapped data from the memory device, for writing, in a second mode, to the memory device, wherein the second set of data includes the set of data, and the first mode and the second mode correspond to different modes of writing to the memory device.

Abstract: Techniques are disclosed for reducing an injection type of program disturb in a memory device. In one aspect, a discharge operation is performed at the start of a program loop. This operation discharges residue electrons from the channel region on the source side of the selected word line, WLn, to the channel region on the drain side of WLn. As a result, in a subsequent channel pre-charge operation, the residue electrons can be more easily removed from the channel. The discharge operation involves applying a voltage pulse to WLn and a first set of drain-side word lines which is adjacent to WLn. The remaining unselected word lines may be held at ground during the voltage pulse.

Abstract: Techniques are described for detecting a short circuit between a word line and a source line in a memory device, and to a method for recovering from such a short circuit. In one aspect, the short circuit is detected in a program operation when a selected word line completes programming after an unusually low number of program loops. A further check is performed to confirm that there is a short circuit. The short circuited word line is then erased and a recovery read is performed for previously-programmed word lines. In another aspect, a short circuit is detected in a read operation.

Abstract: Methods and systems for improving the reliability of stored data in the presence of cross-temperature variation are described. To reduce the number of data errors caused by cross-temperature variation, two or more sensing passes may be performed corresponding with two or more different sensing times. The amount of shifting in the memory cell threshold voltages may be determined on a per-bit basis or on a cell-by-cell basis based on the sensing operations performed during the two or more sensing passes. The stored data states may be assigned based on the amount of shifting in the memory cell threshold voltages during the two or more sensing passes and the type of cross-temperature variation present (e.g., whether the memory cells were programmed at a temperature above 65 degrees Celsius and read back at a temperature below 25 degrees Celsius).

Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.

Abstract: Systems, methods, and devices of the various embodiments provide both “string-sharing” drain select gate electrodes and “string-selective” drain select gate electrodes in vertical NAND strings. Various embodiments may provide two or more vertical NAND strings sharing a common drain select gate electrode while also having separate additional drain select gate electrodes not electrically connected across the two or more vertical NAND strings.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for dynamic read table generation. One apparatus includes a set of non-volatile storage cells. A controller for a set of non-volatile storage cells is configured to, in response to unsuccessfully reading a storage cell of the set of non-volatile storage cells using a parameter, read the storage cell using one or more shifted values. A controller for a set of non-volatile storage cells is configured to, in response to successfully reading a storage cell using one or more shifted values, add the one or more shifted values to a storage device.

Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.

Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.

Abstract: Methods and systems for improving the reliability of stored data in the presence of cross-temperature variation are described. To reduce the number of data errors caused by cross-temperature variation, two or more sensing passes may be performed corresponding with two or more different sensing times. The amount of shifting in the memory cell threshold voltages may be determined on a per-bit basis or on a cell-by-cell basis based on the sensing operations performed during the two or more sensing passes. The stored data states may be assigned based on the amount of shifting in the memory cell threshold voltages during the two or more sensing passes and the type of cross-temperature variation present (e.g., whether the memory cells were programmed at a temperature above 65 degrees Celsius and read back at a temperature below 25 degrees Celsius).