Patents by Inventor Henry Packard Moreton

Henry Packard Moreton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140176588
    Abstract: A graphics processing unit includes a set of geometry processing units each configured to process graphics primitives in parallel with one another. A given geometry processing unit generates one or more graphics primitives or geometry objects and buffers the associated vertex data locally. The geometry processing unit also buffers different sets of indices to those vertices, where each such set represents a different graphics primitive or geometry object. The geometry processing units may then stream the buffered vertices and indices to global buffers in parallel with one another. A stream output synchronization unit coordinates the parallel streaming of vertices and indices by providing each geometry processing unit with a different base address within a global vertex buffer where vertices may be written. The stream output synchronization unit also provides each geometry processing unit with a different base address within a global index buffer where indices may be written.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, JR., Ziyad S. Hakura, Henry Packard MORETON
  • Publication number: 20140176589
    Abstract: A graphics processing unit includes a set of geometry processing units each configured to process graphics primitives in parallel with one another. A given geometry processing unit generates one or more graphics primitives or geometry objects and buffers the associated vertex data locally. The geometry processing unit also buffers different sets of indices to those vertices, where each such set represents a different graphics primitive or geometry object. The geometry processing units may then stream the buffered vertices and indices to global buffers in parallel with one another. A stream output synchronization unit coordinates the parallel streaming of vertices and indices by providing each geometry processing unit with a different base address within a global vertex buffer where vertices may be written. The stream output synchronization unit also provides each geometry processing unit with a different base address within a global index buffer where indices may be written.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, JR., Ziyad S. Hakura, Henry Packard MORETON
  • Patent number: 8751771
    Abstract: One embodiment of the present invention sets forth a technique providing an optimized way to allocate and access memory across a plurality of thread/data lanes. Specifically, the device driver receives an instruction targeted to a memory set up as an array of structures of arrays. The device driver computes an address within the memory using information about the number of thread/data lanes and parameters from the instruction itself. The result is a memory allocation and access approach where the device driver properly computes the target address in the memory. Advantageously, processing efficiency is improved where memory in a parallel processing subsystem is internally stored and accessed as an array of structures of arrays, proportional to the SIMT/SIMD group width (the number of threads or lanes per execution group).
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: June 10, 2014
    Assignee: NVIDIA Corporation
    Inventors: Brian Fahs, Henry Packard Moreton, Brett W. Coon, Kathleen Elliott Nickolls
  • Publication number: 20140118351
    Abstract: A system, method, and computer program product are provided for inputting modified coverage data into a pixel shader. In use, coverage data modified by a depth/stencil test is input into a pixel shader. Additionally, one or more actions are performed at the pixel shader, utilizing the modified coverage data.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 1, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Yury Uralsky, Henry Packard Moreton
  • Patent number: 8698802
    Abstract: One embodiment of the present invention sets forth technique for watertight tessellation in a displaced subdivision surface. A subdivision surface is represented as a novel parametric quad patch that is continuous with respect to position (C0) and partial derivatives (C1) along boundaries as well as interior regions. The novel parametric quad patch is referred to herein as a Hermite Gregory patch and comprises a Hermite patch augmented to include a pair of twist vector parameters per vertex. Each pair of twist vectors is combined into one twist vector during evaluation, according to weights based on proximity to parametric boundaries. Evaluation yields an approximation mesh comprising a position for each vertex and a corresponding normal vector for the vertex. Displacement is performed based on the approximation mesh and a displacement map to generate a displaced approximation mesh that is reflective of the displaced subdivision surface.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: April 15, 2014
    Assignee: Nvidia Corporation
    Inventors: Henry Packard Moreton, Ignacio Castaño Aguado, Kirill Dmitriev
  • Patent number: 8605085
    Abstract: One embodiment of the present invention sets forth a technique for warping uniformly generated barycentric parameters to compensate for perspective foreshortening during tessellation of a geometric object. Near and far step sizes are computed for each edge of the geometric object. A warp equation is associated with each edge. Coefficients for each warp equation are computed from near and far step size for a corresponding edge. Uniformly generated barycentric parameters for each edge comprise an input variable for each corresponding warp equation. Warp equation outputs for edges of the geometric object are blended together using a linear blend function to generate vertices comprising geometric tessellation samples from the geometric object.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: December 10, 2013
    Assignee: NVIDIA Corporation
    Inventor: Henry Packard Moreton
  • Patent number: 8570324
    Abstract: One embodiment of the present invention sets forth technique for watertight evaluation of Gregory patches for Catmull-Clark subdivision surfaces. Each boundary of each patch within a subdivision surface is configured to be owned by one related patch. In general, a given patch may own specific control points for the patch, while certain other control points for the patch may need to be reconstructed because the control points are owned by an adjacent patch. For a given patch, each control point along to a shared boundary is consistently generated using reconstruction data available to the patch. The reconstruction data is generated from values associated with a patch that owns the shared boundary. Because numerically identical data is used to evaluate each patch at each boundary, the boundaries are watertight. One advantage of the present invention is that watertight evaluation may be achieved using similar computational effort versus conventional non-watertight evaluation techniques.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: October 29, 2013
    Assignee: NVIDIA Corporation
    Inventors: Kirill Dmitriev, Henry Packard Moreton
  • Patent number: 8558833
    Abstract: One embodiment of the present invention sets forth a technique for consistently evaluating geometric patches with shared boundaries using barycentric coordinates. A barycentric parameter is generated and represented using a fixed-point fraction. The barycentric parameter is then used to generate a fixed-point barycentric coordinate. The fixed-point barycentric coordinate is then converted to a floating-point representation for evaluating the geometric patches. Computing shared boundary splits using fixed-point fractions eliminates inconsistencies in associated barycentric coordinates due to round-off errors. Evaluating geometric patch equations using consistent barycentric coordinates facilitates precise, consistent computation of vertices along shared boundaries.
    Type: Grant
    Filed: October 14, 2009
    Date of Patent: October 15, 2013
    Assignee: Nvidia Corporation
    Inventor: Henry Packard Moreton
  • Patent number: 8482567
    Abstract: A line rasterization technique in accordance with one embodiment includes conditioning a line by pulling in the ending vertex of the line or pushing out the starting vertex of the line. Thereafter, if the line exits a diamond test area of each pixel that it touches, the pixel may be lit.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: July 9, 2013
    Assignee: Nvidia Corporation
    Inventors: Henry Packard Moreton, Franklin C. Crow
  • Patent number: 8473750
    Abstract: A bridge is disclosed having a security engine to protect digital content at insecure interfaces of the bridge. The bridge permits cryptographic services to he offloaded from a central processing unit to the bridge. The bridge receives a clear text input from a central processing unit. The bridge encrypts the clear text input as cipher text for storage in a memory. The bridge provided the cipher text to a graphics processing unit.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: June 25, 2013
    Assignee: Nvidia Corporation
    Inventors: Michael Brian Cox, Henry Packard Moreton, Brian Keith Langendorf, David G. Reed
  • Patent number: 8373717
    Abstract: The symmetrical properties of a group of vertices are leveraged to reconstruct the group using vertex data for a subset of the vertices and a set of control data. The subset of vertices is symmetrical to one or more other subsets of vertices in the group, and the control data includes information to reconstruct the one or more other subsets using the vertex data for the first set of vertices and symmetrical characteristics of the group. In some embodiments, reconstruction is performed using a geometry shader in a graphics processor to compute the additional vertices.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: February 12, 2013
    Assignee: NVIDIA Corporation
    Inventors: William Orville Ramey, II, Henry Packard Moreton, Douglas H. Rogers
  • Patent number: 8212825
    Abstract: One embodiment of the present invention sets forth a technique for more effectively utilizing graphics hardware by allowing the developer to exploit parallelism at the primitive-level. In this technique, an algorithm is analyzed to break the total work associated with processing one primitive into discrete portions of work. The results of this analysis are used to program a geometry shader group that includes multiple geometry shaders. Upon receiving a single input primitive, the geometry shader group launches multiple parallel threads, one thread in each geometry shader in the group corresponding to each discrete portion of work. As each thread completes, the output of the thread is stored in on-chip GPU memory for processing by the next stage in the graphics pipeline. Since the overall work associated with a given input primitive is distributed across multiple threads, the output of each thread is smaller and, thus, the total memory required to implement the algorithm is reduced.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: July 3, 2012
    Assignee: NVIDIA Corporation
    Inventors: Cass W. Everitt, Henry Packard Moreton
  • Publication number: 20120089792
    Abstract: One embodiment of the present invention sets forth a technique providing an optimized way to allocate and access memory across a plurality of thread/data lanes. Specifically, the device driver receives an instruction targeted to a memory set up as an array of structures of arrays. The device driver computes an address within the memory using information about the number of thread/data lanes and parameters from the instruction itself. The result is a memory allocation and access approach where the device driver properly computes the target address in the memory. Advantageously, processing efficiency is improved where memory in a parallel processing subsystem is internally stored and accessed as an array of structures of arrays, proportional to the SIMT/SIMD group width (the number of threads or lanes per execution group).
    Type: Application
    Filed: September 28, 2011
    Publication date: April 12, 2012
    Inventors: Brian FAHS, John R. Nickolls, Kathleen Elliott Nickolls, Henry Packard Moreton, Brett W. Coon
  • Patent number: 8120607
    Abstract: A system and method for stitching a boundary transition region of a patch produces a graphics primitive topology for the boundary transition region of the patch. A first number of vertices is computed for an inside edge of the boundary transition region using a first tessellation level of detail (LOD) of the inside edge. A second number of vertices is computed for an outside edge of the boundary transition region using a second tessellation LOD of the outside edge. A portion of the first number of vertices and the second number of vertices are merged based on a stitching pattern to produce a set of vertices for the boundary transition region. The set of vertices is stitched to produce an ordered list representing the graphics primitive topology.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: February 21, 2012
    Assignee: NVIDIA Corporation
    Inventors: Justin S. Legakis, Henry Packard Moreton
  • Patent number: 8086828
    Abstract: Heterogeneous processors can cooperate for distributed processing tasks in a multiprocessor computing system. Each processor is operable in a “compatible” mode, in which all processors within a family accept the same baseline command set and produce identical results upon executing any command in the baseline command set. The processors also have a “native” mode of operation in which the command set and/or results may differ in at least some respects from the baseline command set and results. Heterogeneous processors with a compatible mode defined by reference to the same baseline can be used cooperatively for distributed processing by configuring each processor to operate in the compatible mode.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: December 27, 2011
    Assignee: NVIDIA Corporation
    Inventors: Henry Packard Moreton, Abraham B.de Waal
  • Patent number: 8085275
    Abstract: A push buffer-related system, method and computer program product are provided. Initially, an entry is obtained from a buffer storage describing a size and location of a portion of a push buffer. To this end, the portion of the push buffer is capable of being retrieved, utilizing the entry from the buffer storage.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: December 27, 2011
    Assignee: NVIDIA Corporation
    Inventors: Jerome F. Duluk, Jr., Paolo E. Sabella, Henry Packard Moreton
  • Publication number: 20110285722
    Abstract: One embodiment of the present invention sets forth a technique for subdividing stroked higher-order curved segments into quadratic Bèzier curve segments. Path stroking may be accelerated when a GPU or other processor is configured to perform the subdivision operations. Cubic Bèzier path segments are subdivided into quadratic Bèzier curve segments and other lower-order segments at key features. The quadratic Bèzier curve segments approximate the cubic Bèzier path segments. A variance metric is computed for each quadratic Bèzier curve segment, and when the variance metric indicates that the quadratic Bèzier curve segment deviates by more than a threshold from the corresponding portion of the cubic Bèzier path segment, the quadratic Bèzier curve segment is further subdivided. The path composed of the quadratic Bèzier curve segments is then stroked by rendering hull geometry that encloses the path.
    Type: Application
    Filed: April 29, 2011
    Publication date: November 24, 2011
    Inventors: Mark J. KILGARD, Henry Packard Moreton
  • Publication number: 20110285719
    Abstract: One embodiment of the present invention sets forth a technique for subdividing stroked higher-order curved segments into quadratic Bèzier curve segments. Path stroking may be accelerated when a GPU or other processor is configured to perform the subdivision operations. Cubic Bèzier path segments are subdivided into quadratic Bèzier curve segments and other lower-order segments at key features. The quadratic Bèzier curve segments approximate the cubic Bèzier path segments. A variance metric is computed for each quadratic Bèzier curve segment, and when the variance metric indicates that the quadratic Bèzier curve segment deviates by more than a threshold from the corresponding portion of the cubic Bèzier path segment, the quadratic Bèzier curve segment is further subdivided. The path composed of the quadratic Bèzier curve segments is then stroked by rendering hull geometry that encloses the path.
    Type: Application
    Filed: April 6, 2011
    Publication date: November 24, 2011
    Inventors: Mark J. KILGARD, Henry Packard MORETON
  • Publication number: 20110085736
    Abstract: One embodiment of the present invention sets forth technique for watertight evaluation of Gregory patches for Catmull-Clark subdivision surfaces. Each boundary of each patch within a subdivision surface is configured to be owned by one related patch. In general, a given patch may own specific control points for the patch, while certain other control points for the patch may need to be reconstructed because the control points are owned by an adjacent patch. For a given patch, each control point along to a shared boundary is consistently generated using reconstruction data available to the patch. The reconstruction data is generated from values associated with a patch that owns the shared boundary. Because numerically identical data is used to evaluate each patch at each boundary, the boundaries are watertight. One advantage of the present invention is that watertight evaluation may be achieved using similar computational effort versus conventional non-watertight evaluation techniques.
    Type: Application
    Filed: June 30, 2010
    Publication date: April 14, 2011
    Applicant: NVIDIA Corporation
    Inventors: Kirill Dmitriev, Henry Packard Moreton
  • Publication number: 20110081100
    Abstract: One embodiment of the present invention sets forth a technique controlling the pixel location at which the plane equation is evaluated. Multiple pixel offsets (dx, dy) may be specified that each define to a sub-pixel sample position. Attributes are then calculated for each sub-pixel sample position that is covered by a geometric primitive. One advantage of the technique is that anti-aliasing quality may be improved since high frequency color components may be selectively supersampled for particular geometric primitives.
    Type: Application
    Filed: October 5, 2010
    Publication date: April 7, 2011
    Inventors: John Erik Lindholm, Henry Packard Moreton, Ming Y. Siu, Stuart F. Oberman