Abstract: One embodiment of the present invention sets forth technique for watertight tessellation in a displaced subdivision surface. A subdivision surface is represented as a novel parametric quad patch that is continuous with respect to position (C0) and partial derivatives (C1) along boundaries as well as interior regions. The novel parametric quad patch is referred to herein as a Hermite Gregory patch and comprises a Hermite patch augmented to include a pair of twist vector parameters per vertex. Each pair of twist vectors is combined into one twist vector during evaluation, according to weights based on proximity to parametric boundaries. Evaluation yields an approximation mesh comprising a position for each vertex and a corresponding normal vector for the vertex. Displacement is performed based on the approximation mesh and a displacement map to generate a displaced approximation mesh that is reflective of the displaced subdivision surface.

Abstract: A digital content system is disclosed. A security engine disposed in a bridge provides cryptographic services. Clear text digital data received from a central processing unit is encrypted and transferred via the bridge over unsecured data paths as cipher text.

Abstract: Systems and methods for producing anti-aliased images use a sub-pixel sample pattern set that includes two or more unique sub-pixel sample patterns that are complementary. The sub-pixel sample patterns are offset from each pixel center and used to produce images that are combined to produce the anti-aliased image. In addition to providing sub-pixel coverage information, the sub-pixel sample pattern sets may be used to produce sub-pixel shading information. Furthermore, the sub-pixel sample pattern sets may be used in single processor systems or in multiprocessor systems to produce anti-aliased images.

Abstract: A method for providing state inheritance across command lists in a multi-threaded processing environment. The method includes receiving an application program that includes a plurality of parallel threads; generating a command list for each thread of the plurality of parallel threads; causing a first command list associated with a first thread of the plurality of parallel threads to be executed by a processing unit; and causing a second command list associated with a second thread of the plurality of parallel threads to be executed by the processing unit, where the second command list inherits from the first command list state associated with the processing unit.

Abstract: A method for providing state inheritance across command lists in a multi-threaded processing environment. The method includes receiving an application program that includes a plurality of parallel threads; generating a command list for each thread of the plurality of parallel threads; causing a first command list associated with a first thread of the plurality of parallel threads to be executed by a processing unit; and causing a second command list associated with a second thread of the plurality of parallel threads to be executed by the processing unit, where the second command list inherits from the first command list state associated with the processing unit.

Abstract: Systems and methods for using multiple versions of programmable constants within a multi-threaded processor allow a programmable constant to be changed before a program using the constants has completed execution. Processing performance may be improved since programs using different values for a programmable constant may execute simultaneously. The programmable constants are stored in a constant buffer and an entry of a constant buffer table is bound to the constant buffer. When a programmable constant is changed it is copied to an entry in a page pool and address translation for the page pool is updated to correspond to the old version (copy) of the programmable constant. An advantage is that the constant buffer stores the newest version of the programmable constant.

Abstract: Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping engine and an output unit connected to the clipping engine. The clipping engine is configured to clip an input graphics primitive with respect to a set of clipping planes to derive spatial attributes of new vertices. The output unit is configured to identify a subset of the new vertices that defines an output graphics primitive, and the output unit is configured to derive non-spatial attributes of the subset of the new vertices to produce the output graphics primitive.

Abstract: A system and method for performing tessellation in a single pass through a graphics processor divides the processing resources within the graphics processor into sets for performing different tessellation operations. Vertex data and tessellation parameters are routed directly from one processing resource to another instead of being stored in memory. Therefore, a surface patch description is provided to the graphics processor and tessellation is completed in a single uninterrupted pass through the graphics processor without storing intermediate data in memory.

Abstract: A graphics pipeline rasterizes primitives and generates a stream of groups of pixels, such as a stream of pixel quads. A tile coalesce unit received the stream of groups of pixels and generates pixel tiles for use by downstream pixel processing units. The pixel tiles facilitate hazard checks and transaction coherency.

Abstract: Heterogeneous processors can cooperate for distributed processing tasks in a multiprocessor computing system. Each processor is operable in a “compatible” mode, in which all processors within a family accept the same baseline command set and produce identical results upon executing any command in the baseline command set. The processors also have a “native” mode of operation in which the command set and/or results may differ in at least some respects from the baseline command set and results. Heterogeneous processors with a compatible mode defined by reference to the same baseline can be used cooperatively for distributed processing by configuring each processor to operate in the compatible mode.

Abstract: Heterogeneous processors can cooperate for distributed processing tasks in a multiprocessor computing system. Each processor is operable in a “compatible” mode, in which all processors within a family accept the same baseline command set and produce identical results upon executing any command in the baseline command set. The processors also have a “native” mode of operation in which the command set and/or results may differ in at least some respects from the baseline command set and results. Heterogeneous processors with a compatible mode defined by reference to the same baseline can be used cooperatively for distributed processing by configuring each processor to operate in the compatible mode.

Abstract: A graphics processing apparatus coalesces groups of primitives for concurrent processing in a pixel shader. In one implementation, the shader concurrently processes coalesced groups for multisampling. In another implementation, the shader concurrently processes coalesced groups to calculate derivative information.

Abstract: A pixel processing unit reduces the number of pixels exterior to a primitive that must be rendered solely for the purpose of generating texture derivative information required to shade pixels within the primitive. In one embodiment, the alignment of group footprints is selected to reduce pixels exterior to primitives which must be calculated to generate texture derivatives. In another embodiment pairs of primitives from the same graphical surface sharing a common boundary are coalesced and shaded concurrently.

Abstract: A geometry shader of a graphics processor is configured to generate at least a portion of a particle system. The geometry shader receives vertex data including a reference set of vertices. The geometry shader also receives control data including information on how to create additional vertices for the particle system using the vertex data. The geometry shader processes the vertex data and control data to generate the additional vertices for the particle system. In some embodiments, the control data also includes information on other attributes of the generated vertices.

Abstract: A geometry shader of a graphics processor decompresses a set of vertex data representing a simplified model to create a more detailed representation. The geometry shader receives vertex data including a number of vertices representative of a simplified model. The geometry shader decompresses the vertex data by computing additional vertices to create the more detailed representation. In some embodiments, the geometry shader also receives rules data including information on how the vertex data is to be decompressed.

Abstract: The symmetrical properties of a group of vertices are leveraged to reconstruct the group using vertex data for a subset of the vertices and a set of control data. The subset of vertices is symmetrical to one or more other subsets of vertices in the group, and the control data includes information to reconstruct the one or more other subsets using the vertex data for the first set of vertices and symmetrical characteristics of the group. In some embodiments, reconstruction is performed using a geometry shader in a graphics processor to compute the additional vertices.

Abstract: Apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a clipping module includes a mapping unit and a clipping engine that is connected to the mapping unit. The mapping unit is configured to map a graphics primitive onto a canonical representation that is defined with respect to a clipping plane. The clipping engine is configured to clip the graphics primitive with respect to the clipping plane based on the canonical representation.

Abstract: The VPC unit and setup unit of a graphics processing subsystem perform culling operations. The VPC unit performs culling operations on geometric primitives falling within a specific criteria, such as having a property within of a numerical range limit. This limit reduces the complexity of the VPC unit. As increasing rendering complexity typically produces a large number of small primitives, the VPC unit culls many primitives despite its limitations. The VPC unit also includes a cache for storing previously processed vertices in their transformed form, along with previously computed culling information. This increases the VPC unit throughput by reducing the number of memory accesses and culling operations to be performed. The setup unit performs culling operations on any general primitive that cannot be culled by the VPC unit. By performing a first series of culling operations in the VPC unit, the processing burden on the setup unit is decreased.

Abstract: A graphics pipeline has at least one stage that determines operations to be performed on graphics data based at least in part on data processing attributes associated with the graphics data. One application is to permit one or more operations in a stage to be bypassed. Another application is a multi-function stage in which the data operations that are performed depend at least in part on the data type.

Abstract: Clipping techniques introduce additional vertices into existing primitives without requiring creation of new primitives. For an input triangle with one vertex on the invisible side of a clipping surface, a quadrangle can be defined. The vertices of the quadrangle are the two internal vertices of the input triangle and two clipped vertices. For determining attribute values for pixel shading, three vertices of the quadrangle are selected, and a parameter value for an attribute equation is computed using the three selected vertices. For determining pixel coverage for the quadrangle, the three edges that do not correspond to the edge created by clipping are used.