Patents by Inventor Hidekazu Tsuchida
Hidekazu Tsuchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8367510Abstract: In a bipolar silicon carbide semiconductor device in which an electron and a hole recombine with each other during current passage within a silicon carbide epitaxial film grown from a surface of a silicon carbide single crystal substrate, an object described herein is the reduction of defects which are the nuclei of a stacking fault which is expanded by current passage, thereby suppressing the increase of the forward voltage of the bipolar silicon carbide semiconductor device. In a method for producing a bipolar silicon carbide semiconductor device, the device is subjected to a thermal treatment at a temperature of 300° C. or higher in the final step of production. Preferably, the above-mentioned thermal treatment is carried out after the formation of electrodes and then the resulting bipolar silicon carbide semiconductor device is mounted in a package.Type: GrantFiled: September 1, 2006Date of Patent: February 5, 2013Assignee: Central Research Institute of Electric Power IndustryInventors: Toshiyuki Miyanagi, Hidekazu Tsuchida, Isaho Kamata, Masahiro Nagano, Yoshitaka Sugawara, Koji Nakayama, Ryosuke Ishii
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Publication number: 20130009170Abstract: An epitaxial SiC single crystal substrate including a SiC single crystal wafer whose main surface is a c-plane or a surface that inclines a c-plane with an angle of inclination that is more than 0 degree but less than 10 degrees, and SiC epitaxial film that is formed on the main surface of the SiC single crystal wafer, wherein the dislocation array density of threading edge dislocation arrays that are formed in the SiC epitaxial film is 10 arrays/cm2 or less.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicants: SHOWA DENKO K.K., CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRY, NATIONAL INSTITUTE OF ADVANCE INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Kenji MOMOSE, Michiya ODAWARA, Keiichi MATSUZAWA, Hajime OKUMURA, Kazutoshi KOJIMA, Yuuki ISHIDA, Hidekazu TSUCHIDA, Isaho KAMATA
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Publication number: 20120325138Abstract: A film-forming apparatus and method comprising a film-forming chamber for supplying a reaction gas into, a cylindrical shaped liner provided between an inner wall of the film-forming chamber and a space for performing a film-forming process, a main-heater for heating a substrate placed inside the liner, from the bottom side, a sub-heater cluster provided between the liner and the inner wall, for heating the substrate from the top side, wherein the main-heater and the sub-heater cluster are resistive heaters, wherein the sub-heater cluster has a first sub-heater provided at the closest position to the substrate, and a second sub-heater provided above the first sub-heater, wherein the first sub-heater heats the substrate in combination with the main-heater, the second sub-heater heats the liner at a lower output than the first sub-heater, wherein each temperature of the main-heater, the first sub-heater, and the second sub-heater is individually controlled.Type: ApplicationFiled: June 19, 2012Publication date: December 27, 2012Applicants: NuFlare Techology, Inc., Toyota Jidosha Kabushiki Kaisha, Denso Corporation, Central Res. Institute of Electric Power IndustryInventors: Kunihiko SUZUKI, Hideki Ito, Naohisa Ikeya, Hidekazu Tsuchida, Isaho Kamata, Masahiko Ito, Masami Naito, Hiroaki Fujibayashi, Ayumu Adachi, Koichi Nishikawa
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Patent number: 8293623Abstract: An epitaxial SiC single crystal substrate including a SiC single crystal wafer whose main surface is a c-plane or a surface that inclines a c-plane with an angle of inclination that is more than 0 degree but less than 10 degrees, and SiC epitaxial film that is formed on the main surface of the SiC single crystal wafer, wherein the dislocation array density of threading edge dislocation arrays that are formed in the SiC epitaxial film is 10 arrays/cm2 or less.Type: GrantFiled: September 12, 2008Date of Patent: October 23, 2012Assignees: Showa Denko K.K., National Institute of Advanced Industrial Science and Technology, Central Research Institute of Electric Power IndustryInventors: Kenji Momose, Michiya Odawara, Keiichi Matsuzawa, Hajime Okumura, Kazutoshi Kojima, Yuuki Ishida, Hidekazu Tsuchida, Isaho Kamata
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Patent number: 8178949Abstract: Bipolar semiconductor devices have a Zener voltage controlled very precisely in a wide range of Zener voltages (for example, from 10 to 500 V). A bipolar semiconductor device has a mesa structure and includes a silicon carbide single crystal substrate of a first conductivity type, a silicon carbide conductive layer of a first conductivity type, a highly doped layer of a second conductivity type and a silicon carbide conductive layer of a second conductivity type which substrate and conductive layers are laminated in the order named.Type: GrantFiled: January 31, 2008Date of Patent: May 15, 2012Assignees: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Ryosuke Ishii, Koji Nakayama, Yoshitaka Sugawara, Hidekazu Tsuchida
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Patent number: 8178940Abstract: An intermediate metal film is formed between a Schottky electrode and a pad electrode. A Schottky barrier height between the intermediate metal film and a silicon carbide epitaxial film is equivalent to or higher than a Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film. By this configuration, an excess current and a leak current through a pin-hole can be suppressed even in the case in which a Schottky barrier height between the pad electrode and the silicon carbide epitaxial film is less than the Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film.Type: GrantFiled: November 22, 2006Date of Patent: May 15, 2012Assignee: Central Research Institute of Electric Power IndustryInventors: Tomonori Nakamura, Hidekazu Tsuchida, Toshiyuki Miyanagi
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Patent number: 8154026Abstract: In a SiC bipolar semiconductor device with a mesa structure having a SiC drift layer of a first conductive type and a SiC carrier injection layer of a second conductive type that are SiC epitaxial layers grown from a surface of a SiC single crystal substrate, the formation of stacking faults and the expansion of the area thereof are prevented and thereby the increase in forward voltage is prevented. Further, a characteristic of withstand voltage in a reverse biasing is improved. An forward-operation degradation preventing layer is formed on a mesa wall or on a mesa wall and a mesa periphery to separate spatially the surface of the mesa wall from a pn-junction interface. In one embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide low resistance layer of a second conductive type that is equipotential during the application of a reverse voltage.Type: GrantFiled: December 13, 2006Date of Patent: April 10, 2012Assignee: Central Research Institute of Electric Power IndustryInventors: Ryosuke Ishii, Koji Nakayama, Yoshitaka Sugawara, Toshiyuki Miyanagi, Hidekazu Tsuchida, Isaho Kamata, Tomonori Nakamura
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Patent number: 8093599Abstract: A silicon carbide Zener diode is a bipolar semiconductor device that has a mesa structure and includes a silicon carbide single crystal substrate of a first conductivity type, formed thereon, a silicon carbide conductive layer of a first conductivity type, and a silicon carbide conductive layer of a second conductivity type formed on the silicon carbide conductive layer of a first conductivity type, wherein a depletion layer that is formed under reverse bias at a junction between the silicon carbide conductive layer of a first conductivity type and the silicon carbide conductive layer of a second conductivity type does not reach a mesa corner formed in the silicon carbide conductive layer of a first conductivity type.Type: GrantFiled: April 25, 2008Date of Patent: January 10, 2012Assignee: Central Research Institute of Electric Power IndustryInventors: Ryosuke Ishii, Koji Nakayama, Yoshitaka Sugawara, Hidekazu Tsuchida
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Patent number: 7960738Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: GrantFiled: June 21, 2010Date of Patent: June 14, 2011Assignees: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Patent number: 7960257Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: GrantFiled: June 21, 2010Date of Patent: June 14, 2011Assignees: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Patent number: 7960737Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: GrantFiled: June 21, 2010Date of Patent: June 14, 2011Assignees: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Patent number: 7902054Abstract: A silicon carbide Schottky barrier semiconductor device provided with a Ta electrode as a Schottky electrode, in which the Schottky barrier height is controlled to a desired value in a range where power loss is minimized without increasing the n factor. The method for manufacturing the silicon carbide Schottky barrier semiconductor device includes the steps of depositing Ta on a crystal face of an n-type silicon carbide epitaxial film, the crystal face having an inclined angle in the range of 0° to 10° from a (000-1) C face, and carrying out a thermal treatment at a temperature range of 300 to 1200° C. to form the Schottky electrode.Type: GrantFiled: February 15, 2007Date of Patent: March 8, 2011Assignee: Central Research Institute of Electric Power IndustryInventors: Hidekazu Tsuchida, Tomonori Nakamura, Toshiyuki Miyanagi
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Publication number: 20110006309Abstract: An epitaxial SiC single crystal substrate including a SiC single crystal wafer whose main surface is a c-plane or a surface that inclines a c-plane with an angle of inclination that is more than 0 degree but less than 10 degrees, and SiC epitaxial film that is formed on the main surface of the SiC single crystal wafer, wherein the dislocation array density of threading edge dislocation arrays that are formed in the SiC epitaxial film is 10 arrays/cm2 or less.Type: ApplicationFiled: September 12, 2008Publication date: January 13, 2011Applicant: SHOWA DENKO K.K.Inventors: Kenji Momose, Michiya Odawara, Keiichi Matsuzawa, Hajime Okumura, Kazutoshi Kojima, Yuuki Ishida, Hidekazu Tsuchida, Isaho Kamata
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Patent number: 7834362Abstract: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers by high temperature annealing and a SiC semiconductor device fabricated by the method. The method for improving the quality of a SiC layer by eliminating or reducing some carrier trapping centers includes the steps of: (a) carrying out ion implantation of carbon atom interstitials (C), silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer (A) of the starting SiC crystal layer (E) to introduce excess carbon interstitials into the implanted surface layer, and (b) heating the layer for making the carbon interstitials (C) to diffuse out from the implanted surface layer (A) into a bulk layer (E) and for making the electrically active point defects in the bulk layer inactive. After the above steps, the surface layer (A) can be etched or mechanically removed. The SiC semiconductor device is fabricated by the method.Type: GrantFiled: October 14, 2008Date of Patent: November 16, 2010Assignee: Central Research Institute of Electric Power IndustryInventors: Hidekazu Tsuchida, Liutauras Storasta
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Publication number: 20100261333Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: ApplicationFiled: June 21, 2010Publication date: October 14, 2010Applicants: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Publication number: 20100258816Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: ApplicationFiled: June 21, 2010Publication date: October 14, 2010Applicants: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Joji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Publication number: 20100258817Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: ApplicationFiled: June 21, 2010Publication date: October 14, 2010Applicants: The Kansai Electric Power Co., Inc., Central Research Institute of Electric Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Patent number: 7768017Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: GrantFiled: December 1, 2004Date of Patent: August 3, 2010Assignees: The Kansai Electric Co., Inc., Central Research Institution of Electrical Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Patent number: 7754589Abstract: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers in the as-grown SiC crystal. The method includes the steps of: (a) carrying out ion implantation of carbon atoms, silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer of the SiC crystal layer to introduce carbon interstitials into the surface layer, and (b) growing the SiC layer upward from the edge face of the surface layer into which the carbon interstitials have been introduced, and diffusing out the carbon interstitials that have been introduced into the surface layer from the surface layer into the grown layer and combining the carbon interstitials and point defects to make the electrically active point defects in the grown layer inactive.Type: GrantFiled: October 15, 2008Date of Patent: July 13, 2010Assignee: Central Research Institute of Electric Power IndustryInventors: Hidekazu Tsuchida, Liutauras Storasta
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Publication number: 20100173475Abstract: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers in the as-grown SiC crystal. The method includes the steps of: (a) carrying out ion implantation of carbon atoms, silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer of the SiC crystal layer to introduce carbon interstitials into the surface layer, and (b) growing the SiC layer upward from the edge face of the surface layer into which the carbon interstitials have been introduced, and diffusing out the carbon interstitials that have been introduced into the surface layer from the surface layer into the grown layer and combining the carbon interstitials and point defects to make the electrically active point defects in the grown layer inactive.Type: ApplicationFiled: March 16, 2010Publication date: July 8, 2010Applicant: Central Research Institute of Electric Power IndustryInventors: Hidekazu Tsuchida, Liutauras Storasta