Patents by Inventor Hidekazu Tsuchida
Hidekazu Tsuchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7737011Abstract: It is an object to provide a method for improving the quality of an SiC layer by effectively reducing or eliminating the carrier trapping centers by high temperature annealing and an SiC semiconductor device fabricated by the method. A method for improving the quality of an SiC layer by eliminating or reducing some carrier trapping centers comprising the steps of: (a) carrying out ion implantation of carbon atoms (C), silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer (A) of the starting SiC crystal layer (E) to introduce excess carbon interstitials into the implanted surface layer, and (b) heating the layer for making the carbon interstitials (C) to diffuse out from the implanted surface layer (A) into a bulk layer (E) and for making the electrically active point defects in the bulk layer inactive. After the above steps, the surface layer (A) can be etched or mechanically removed. A semiconductor device according to the invention is fabricated by the method.Type: GrantFiled: November 10, 2006Date of Patent: June 15, 2010Assignee: Central Research Institute of Electric Power IndustryInventors: Hidekazu Tsuchida, Liutauras Storasta
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Publication number: 20100084663Abstract: A silicon carbide Zener diode is a bipolar semiconductor device that has a mesa structure and includes a silicon carbide single crystal substrate of a first conductivity type, formed thereon, a silicon carbide conductive layer of a first conductivity type, and a silicon carbide conductive layer of a second conductivity type formed on the silicon carbide conductive layer of a first conductivity type, wherein a depletion layer that is formed under reverse bias at a junction between the silicon carbide conductive layer of a first conductivity type and the silicon carbide conductive layer of a second conductivity type does not reach a mesa corner formed in the silicon carbide conductive layer of a first conductivity type.Type: ApplicationFiled: April 25, 2008Publication date: April 8, 2010Applicant: Central Research Institute of Electric PowerInventors: Ryosuke Ishii, Koji Nakayama, Yoshitaka Sugawara, Hidekazu Tsuchida
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Publication number: 20100032686Abstract: Bipolar semiconductor devices have a Zener voltage controlled very precisely in a wide range of Zener voltages (for example, from 10 to 500 V). A bipolar semiconductor device has a mesa structure and includes a silicon carbide single crystal substrate of a first conductivity type, a silicon carbide conductive layer of a first conductivity type, a highly doped layer of a second conductivity type and a silicon carbide conductive layer of a second conductivity type which substrate and conductive layers are laminated in the order named.Type: ApplicationFiled: January 31, 2008Publication date: February 11, 2010Applicants: THE KANSAI ELECTRIC POWER CO., INC., CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRYInventors: Ryosuke Ishii, Koji Nakayama, Yoshitaka Sugawara, Hidekazu Tsuchida
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Publication number: 20090317983Abstract: In a bipolar silicon carbide semiconductor device in which an electron and a hole recombine with each other during current passage within a silicon carbide epitaxial film grown from a surface of a silicon carbide single crystal substrate, an object described herein is the reduction of defects which are the nuclei of a stacking fault which is expanded by current passage, thereby suppressing the increase of the forward voltage of the bipolar silicon carbide semiconductor device. In a method for producing a bipolar silicon carbide semiconductor device, the device is subjected to a thermal treatment at a temperature of 300° C. or higher in the final step of production. Preferably, the above-mentioned thermal treatment is carried out after the formation of electrodes and then the resulting bipolar silicon carbide semiconductor device is mounted in a package.Type: ApplicationFiled: September 1, 2006Publication date: December 24, 2009Applicants: THE KANSAI ELECTRIC POWER CO., INC., CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRYInventors: Toshiyuki Miyanagi, Hidekazu Tsuchida, Isaho Kamata, Masahiro Nagano, Yoshitaka Sugawara, Koji Nakayama, Ryosuke Ishii
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Publication number: 20090243026Abstract: An intermediate metal film is formed between a Schottky electrode and a pad electrode. A Schottky barrier height between the intermediate metal film and a silicon carbide epitaxial film is equivalent to or higher than a Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film. By this configuration, an excess current and a leak current through a pin-hole can be suppressed even in the case in which a Schottky barrier height between the pad electrode and the silicon carbide epitaxial film is less than the Schottky barrier height between the Schottky electrode and the silicon carbide epitaxial film.Type: ApplicationFiled: November 22, 2006Publication date: October 1, 2009Applicant: Central Research Institute of Electric Power IndustryInventors: Tomonori Nakamura, Hidekazu Tsuchida, Toshiyuki Miyanagi
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Publication number: 20090195296Abstract: In a bipolar semiconductor device such that electrons and holes are recombined in a silicon carbide epitaxial film grown from the surface of a silicon carbide single crystal substrate at the time of on-state forward bias operation; an on-state forward voltage increased in a silicon carbide bipolar semiconductor device is recovered by shrinking the stacking fault area enlarged by on-state forward bias operation. In a method of this invention, the bipolar semiconductor device in which the stacking fault area enlarged and the on-state forward voltage has been increased by on-state forward bias operation, is heated at a temperature of higher than 350° C.Type: ApplicationFiled: August 4, 2006Publication date: August 6, 2009Applicants: THE KANSAI ELECTRIC POWER CO., INC., CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRYInventors: Toshiyuki Miyanagi, Hidekazu Tsuchida, Isaho Kamata, Yoshitaka Sugawara, Koji Nakayama, Ryosuke Ishii
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Publication number: 20090096053Abstract: A silicon carbide Schottky barrier semiconductor device provided with a Ta electrode as a Schottky electrode, in which the Schottky barrier height is controlled to a desired value in a range where power loss is minimized without increasing the n factor. The method for manufacturing the silicon carbide Schottky barrier semiconductor device includes the steps of depositing Ta on a crystal face of an n-type silicon carbide epitaxial film, the crystal face having an inclined angle in the range of 0° to 10° from a (000-1) C face, and carrying out a thermal treatment at a temperature range of 300 to 1200° C. to form the Schottky electrode.Type: ApplicationFiled: February 15, 2007Publication date: April 16, 2009Applicant: CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRYInventors: Hidekazu Tsuchida, Tomonori Nakamura, Toshiyuki Miyanagi
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Patent number: 7507650Abstract: A process for producing a Schottky junction type semiconductor device includes the steps of forming a Schottky electrode on a surface of a silicon carbide epitaxial layer, wherein a Schottky electrode made of molybdenum, tungsten, or an alloy thereof is formed on the surface of the silicon carbide epitaxial layer and is subjected to heat treatment so as to induce an alloying reaction at an interface of the silicon carbide epitaxial layer and the Schottky electrode, thereby forming an alloy layer at the interface, whereby the height of a Schottky barrier is controlled while maintaining an n-factor at a nearly constant low value.Type: GrantFiled: March 25, 2005Date of Patent: March 24, 2009Assignee: Central Research Institute of Electric Power IndustryInventors: Tomonori Nakamura, Hidekazu Tsuchida, Toshiyuki Miyanagi
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Publication number: 20090047772Abstract: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers in the as-grown SiC crystal. The method includes the steps of: (a) carrying out ion implantation of carbon atoms, silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer of the SiC crystal layer to introduce carbon interstitials into the surface layer, and (b) growing the SiC layer upward from the edge face of the surface layer into which the carbon interstitials have been introduced, and diffusing out the carbon interstitials that have been introduced into the surface layer from the surface layer into the grown layer and combining the carbon interstitials and point defects to make the electrically active point defects in the grown layer inactive.Type: ApplicationFiled: October 15, 2008Publication date: February 19, 2009Applicant: Central Research Institute of Electric Power IndustryInventors: Hidekazu Tsuchida, Liutauras Storasta
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Publication number: 20090045413Abstract: In a SiC bipolar semiconductor device with a mesa structure having a SiC drift layer of a first conductive type and a SiC carrier injection layer of a second conductive type that are SiC epitaxial layers grown from a surface of a SiC single crystal substrate, the formation of stacking faults and the expansion of the area thereof are prevented and thereby the increase in forward voltage is prevented. Further, a characteristic of withstand voltage in a reverse biasing is improved. An forward-operation degradation preventing layer is formed on a mesa wall or on a mesa wall and a mesa periphery to separate spatially the surface of the mesa wall from a pn-junction interface. In one embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide low resistance layer of a second conductive type that is equipotential during the application of a reverse voltage.Type: ApplicationFiled: December 13, 2006Publication date: February 19, 2009Applicants: THE KANSAI ELECTRIC POWER CO., INC., CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRYInventors: Ryosuke Ishii, Koji Nakayama, Yoshitaka Sugawara, Toshiyuki Miyanagi, Hidekazu Tsuchida, Isaho Kamata, Tomonori Nakamura
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Publication number: 20090039358Abstract: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers by high temperature annealing and a SiC semiconductor device fabricated by the method. The method for improving the quality of a SiC layer by eliminating or reducing some carrier trapping centers includes the steps of: (a) carrying out ion implantation of carbon atom interstitials (C), silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer (A) of the starting SiC crystal layer (E) to introduce excess carbon interstitials into the implanted surface layer, and (b) heating the layer for making the carbon interstitials (C) to diffuse out from the implanted surface layer (A) into a bulk layer (E) and for making the electrically active point defects in the bulk layer inactive. After the above steps, the surface layer (A) can be etched or mechanically removed. The SiC semiconductor device is fabricated by the method.Type: ApplicationFiled: October 14, 2008Publication date: February 12, 2009Applicant: Central Research Institute of Electric Power IndustryInventors: Hidekazu Tsuchida, Liutauras Storasta
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Publication number: 20080026544Abstract: It is an object to provide a method for improving the quality of an SiC layer by effectively reducing or eliminating the carrier trapping centers by high temperature annealing and an SiC semiconductor device fabricated by the method. A method for improving the quality of an SiC layer by eliminating or reducing some carrier trapping centers comprising the steps of: (a) carrying out ion implantation of carbon atoms (C), silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer (A) of the starting SiC crystal layer (E) to introduce excess carbon interstitials into the implanted surface layer, and (b) heating the layer for making the carbon interstitials (C) to diffuse out from the implanted surface layer (A) into a bulk layer (E) and for making the electrically active point defects in the bulk layer inactive. After the above steps, the surface layer (A) can be etched or mechanically removed. A semiconductor device according to the invention is fabricated by the method.Type: ApplicationFiled: November 10, 2006Publication date: January 31, 2008Applicant: Central Research Institute of Electric Power IndustryInventors: Hidekazu Tsuchida, Liutauras Storasta
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Publication number: 20070290211Abstract: A process for manufacturing a bipolar type semiconductor device in which at least a part of a region where an electron and a hole are recombined during current flowing is formed with a silicon carbide epitaxial layer that has been grown from the surface of a silicon carbide substrate, is characterized by that the surface of the silicon carbide substrate is treated by hydrogen etching and the epitaxial layer is then formed by the epitaxial growth of silicon carbide from the treated surface. A propagation of a basal plane dislocation to the epitaxial layer can be further reduced by treating the surface of the silicon carbide substrate by using chemical mechanical polishing and hydrogen etching in this order.Type: ApplicationFiled: March 25, 2005Publication date: December 20, 2007Applicants: The Kansai Electric Power Co., Inc., Cental Research Institute of Electric Power IndustryInventors: Koji Nakayama, Yoshitaka Sugawara, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Publication number: 20070134897Abstract: A process for producing a Schottky junction type semiconductor device includes the steps of forming a Schottky electrode on a surface of a silicon carbide epitaxial layer, wherein a Schottky electrode made of molybdenum, tungsten, or an alloy thereof is formed on the surface of the silicon carbide epitaxial layer and is subjected to heat treatment so as to induce an alloying reaction at an interface of the silicon carbide epitaxial layer and the Schottky electrode, thereby forming an alloy layer at the interface, whereby the height of a Schottky barrier is controlled while maintaining an n-factor at a nearly constant low value.Type: ApplicationFiled: March 25, 2005Publication date: June 14, 2007Applicant: Central Research Institite of Electric Power IndustryInventors: Tomonori Nakamura, Hidekazu Tsuchida, Toshiyuki Miyanagi
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Publication number: 20070090370Abstract: With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle ? of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 ?m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.Type: ApplicationFiled: December 1, 2004Publication date: April 26, 2007Inventors: Koji Nakayama, Yoshitaka Sugawara, Katsunori Asano, Hidekazu Tsuchida, Isaho Kamata, Toshiyuki Miyanagi, Tomonori Nakamura
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Patent number: 7081420Abstract: A process for closing hollow-core defects, called micropipes, during growth by CVD of a SiC crystal on a SiC single crystal substrate having hollow-core defects, and a crystal obtained according to the process, by contacting the SiC crystal with a source gas adjusted to a C/Si atom ratio range in which the crystal growth rate is determined by the carbon atom supply limitation, then epitaxially growing and laminating a plurality of SiC crystal layers, wherein hollow-core defects in the SiC single crystal substrate dissociate into a plurality of dislocations given by small Burghers vector in order not to propagate to the crystal surface. In addition, the present invention provides a fabrication process of a SiC crystal, wherein a first SiC crystal is made as a buffer layer, and a further SiC crystal is layered thereon using a source gas adjusted to be higher than that of the C/Si ratio when forming the buffer layer, whereby a desired film property is conferred.Type: GrantFiled: March 19, 2003Date of Patent: July 25, 2006Assignee: Central Research Institute of Electric Power IndustryInventors: Isaho Kamata, Hidekazu Tsuchida
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Publication number: 20050181627Abstract: A process for closing hollow-core defects, called micropipes, during growth by CVD of a SiC crystal on a SiC single crystal substrate having hollow-core defects, and a crystal obtained according to the process, by contacting the SiC crystal with a source gas adjusted to a C/Si atom ratio range in which the crystal growth rate is determined by the carbon atom supply limitation, then epitaxially growing and laminating a plurality of SiC crystal layers, wherein hollow-core defects in the SiC single crystal substrate dissociate into a plurality of dislocations given by small Burgers vector in order not to propagate to the crystal surface. In addition, the present invention provides a fabrication process of a SiC crystal, wherein a first SiC crystal is made as a buffer layer, and a further SiC crystal is layered thereon using a source gas adjusted to be higher than that of the C/Si ratio when forming the buffer layer, whereby a desired film property is conferred.Type: ApplicationFiled: March 19, 2003Publication date: August 18, 2005Inventors: Isaho Kamata, Hidekazu Tsuchida