Patents by Inventor Hidenobu Nagashima
Hidenobu Nagashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11871578Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.Type: GrantFiled: December 30, 2022Date of Patent: January 9, 2024Assignee: KIOXIA CORPORATIONInventor: Hidenobu Nagashima
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Publication number: 20230354612Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.Type: ApplicationFiled: July 7, 2023Publication date: November 2, 2023Applicant: KIOXIA CORPORATIONInventor: Hidenobu NAGASHIMA
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Publication number: 20230139596Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.Type: ApplicationFiled: December 30, 2022Publication date: May 4, 2023Applicant: KIOXIA CORPORATIONInventor: Hidenobu NAGASHIMA
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Patent number: 11610912Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.Type: GrantFiled: February 24, 2021Date of Patent: March 21, 2023Assignee: KIOXIA CORPORATIONInventor: Hidenobu Nagashima
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Patent number: 11482489Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.Type: GrantFiled: August 11, 2020Date of Patent: October 25, 2022Assignee: KIOXIA CORPORATIONInventors: Shingo Nakajima, Ryota Asada, Hidenobu Nagashima, Masayuki Akou
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Publication number: 20210183881Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.Type: ApplicationFiled: February 24, 2021Publication date: June 17, 2021Applicant: Toshiba Memory CorporationInventor: Hidenobu NAGASHIMA
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Patent number: 10971512Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.Type: GrantFiled: March 30, 2020Date of Patent: April 6, 2021Assignee: Toshiba Memory CorporationInventor: Hidenobu Nagashima
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Publication number: 20200373237Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.Type: ApplicationFiled: August 11, 2020Publication date: November 26, 2020Applicant: Toshiba Memory CorporationInventors: Shingo Nakajima, Ryota Asada, Hidenobu Nagashima, Masayuki Akou
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Patent number: 10777501Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.Type: GrantFiled: July 3, 2018Date of Patent: September 15, 2020Assignee: Toshiba Memory CorporationInventors: Shingo Nakajima, Ryota Asada, Hidenobu Nagashima, Masayuki Akou
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Publication number: 20200227431Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.Type: ApplicationFiled: March 30, 2020Publication date: July 16, 2020Applicant: Toshiba Memory CorporationInventor: Hidenobu NAGASHIMA
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Patent number: 10651190Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.Type: GrantFiled: September 7, 2018Date of Patent: May 12, 2020Assignee: Toshiba Memory CorporationInventor: Hidenobu Nagashima
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Publication number: 20190296034Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.Type: ApplicationFiled: September 7, 2018Publication date: September 26, 2019Applicant: Toshiba Memory CorporationInventor: Hidenobu NAGASHIMA
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Publication number: 20190287894Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.Type: ApplicationFiled: July 3, 2018Publication date: September 19, 2019Applicant: Toshiba Memory CorporationInventors: Shingo NAKAJIMA, Ryota Asada, Hidenobu Nagashima, Masayuki Akou
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Patent number: 9030020Abstract: In one embodiment, a semiconductor memory device includes a substrate, and device regions formed in the substrate to extend in a first direction which is parallel to a principal plane of the substrate. The device further includes select gates disposed on the substrate to extend in a second direction which is perpendicular to the first direction, and a contact region provided between the select gates on the substrate and including contact plugs disposed on the respective device regions. Further, the contact region includes partial regions, in each of which N contact plugs are disposed on N successive device regions to be arranged on a straight line being non-parallel to the first and second directions, where N is an integer of 2 or more. Further, the contact region includes the partial regions of at least two types whose values of N are different.Type: GrantFiled: March 22, 2011Date of Patent: May 12, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiko Kato, Hidenobu Nagashima
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Patent number: 8723245Abstract: According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film.Type: GrantFiled: March 21, 2011Date of Patent: May 13, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Akahori, Kiyohito Nishihara, Masaki Kondo, Yingkang Zhang, Shigeo Kondo, Hidenobu Nagashima, Kazuaki Iwasawa, Takashi Ichikawa
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Publication number: 20140070304Abstract: According to an embodiment, a nonvolatile memory device includes a memory cell string, a control gate, first and second insulating films. The memory cell string includes a semiconductor layer and a plurality of memory cells disposed on the semiconductor layer. The control gate is provided on each of the memory cells. The first insulating film covers each side surface of the memory cells, and a side surface of the control gate. The second insulating film covering an upper portion of the control gate is provided on each of two adjacent memory cells. A first air gap is disposed between the two adjacent memory cells and surround by the first insulating film and the second insulating film, and the semiconductor layer is exposed by the first gap, or thickness of an insulating film between the first gap and the semiconductor layer is thinner than the first insulating film.Type: ApplicationFiled: March 5, 2013Publication date: March 13, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Ken KOMIYA, Tatsuya KATO, Kenta YAMADA, Hidenobu NAGASHIMA
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Patent number: 8592887Abstract: A semiconductor storage device includes an interlayer insulating film provided between select gate electrodes, a first fill material extending along upper portions of memory cell gate electrodes so as to cover air gaps residing between the memory cell gate electrodes, the first fill material extending along sidewalls of the select gate electrodes and sidewalls of the interlayer insulating film so as to define a recess above the first fill material extending along the sidewalls of the select gate electrodes and the sidewalls of the interlayer insulating film, a second fill material filling the recess above the first fill material, and a plurality of contacts formed through the interlayer insulating film, the contacts physically contacting each of device areas formed in a semiconductor substrate.Type: GrantFiled: December 21, 2011Date of Patent: November 26, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Daina Inoue, Hidenobu Nagashima, Akira Yotsumoto
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Patent number: 8294194Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes memory transistors, an interlayer insulating film, a peripheral transistor and a sidewall. The memory transistors are formed on a semiconductor substrate. Each of the memory transistors includes a first stack gate which includes a floating gate electrode, a second gate insulating film, and a control gate electrode. The interlayer insulating film is formed between the first stack gates. The interlayer insulating film includes a first air gap. The peripheral transistor is formed on the substrate. The peripheral transistor includes a second stack gate which includes a first gate electrode, a third gate insulating film, and a second gate electrode. The sidewall is formed on a side surface of the second stack gate and includes a second air gap. An upper end of the second air gap is located at a position lower than the third gate insulating film.Type: GrantFiled: March 21, 2011Date of Patent: October 23, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuhiko Noda, Hidenobu Nagashima
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Publication number: 20120256263Abstract: A semiconductor storage device includes an interlayer insulating film provided between select gate electrodes, a first fill material extending along upper portions of memory cell gate electrodes so as to cover air gaps residing between the memory cell gate electrodes, the first fill material extending along sidewalls of the select gate electrodes and sidewalls of the interlayer insulating film so as to define a recess above the first fill material extending along the sidewalls of the select gate electrodes and the sidewalls of the interlayer insulating film, a second fill material filling the recess above the first fill material, and a plurality of contacts formed through the interlayer insulating film, the contacts physically contacting each of device areas formed in a semiconductor substrate.Type: ApplicationFiled: December 21, 2011Publication date: October 11, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Daina INOUE, Hidenobu Nagashima, Akira Yotsumoto
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Publication number: 20120241838Abstract: According to one embodiment, a semiconductor storage device includes: a plurality of word lines that are formed at predetermined intervals in a first direction on the element region; a select gate transistor that is arranged in each of both sides of the word lines and has a width in the first direction wider than the word line; a first air gap that is positioned between the word lines; and a second air gap that is formed on a side wall portion opposite to a side of the word line of the select gate transistor. Further, according to one embodiment, the semiconductor storage device is provided in which an oxide film is formed on a surface of a substrate between the select gate transistors that are adjacent to each other, and a cross-sectional surface in a direction perpendicular to the first direction under the oxide film has a convex shape.Type: ApplicationFiled: March 16, 2012Publication date: September 27, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Hidenobu NAGASHIMA, Akira YOTSUMOTO