Patents by Inventor Hidenobu Nishikawa
Hidenobu Nishikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20090166064Abstract: The invention includes: applying an anisotropic conductive resin including conductive particles only to a plurality of bumps of an electronic component; placing the electronic component above a main surface of a flexible wiring board via the anisotropic conductive resin; and pressurizing the electronic component to the wiring board and curing the anisotropic conductive resin applied to the plurality of bumps to join the plurality of bumps to the electrodes of the wiring board. This can prevent a defective mounting of the electronic component.Type: ApplicationFiled: January 31, 2007Publication date: July 2, 2009Inventors: Hidenobu Nishikawa, Daido Komyoji
-
Publication number: 20090051606Abstract: An electronic circuit module with a built-in antenna (1) includes the following elements: a mounting module having a wiring board (2), a passive component, and a semiconductor device; a resin sheet substrate (11) having an antenna pattern (12) formed on a first principle surface of a base thereof; and a magnetic layer interposed between the mounting module and the resin sheet substrate (11). These elements are housed in a case (16).Type: ApplicationFiled: April 25, 2007Publication date: February 26, 2009Inventors: Shozo Ochi, Hidenobu Nishikawa, Hiroshi Sakurai
-
Publication number: 20090040734Abstract: The semiconductor memory module incorporating antenna includes a wiring board (11) having a connection terminal (17) connected with a control semiconductor element (16) and arranged at a position exposed to the surface of an outer case (15), and a terminal electrode (18) for antenna connection connected with the control semiconductor element (16) and arranged in the outer case (15); a semiconductor storage element (12) mounted on one side of the wiring board (11); and a loop-like antenna (13) and an antenna terminal electrode (20) formed on the other side of the wiring board (11) along the outer peripheral thereof, the wiring board (11) includes at least one magnetic body layer (14) and the terminal electrode (18) for antenna connection is connected with the antenna terminal electrode (20).Type: ApplicationFiled: March 28, 2007Publication date: February 12, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Shozo Ochi, Hidenobu Nishikawa, Hiroshi Sakurai
-
Publication number: 20090009976Abstract: Memory card includes a circuit board, a component mounted on a main face of the circuit board, casing covering at least the main face of the circuit board and the component, and bittering agent retained in a roughened area provided on casing or an exposed part of the circuit board.Type: ApplicationFiled: January 26, 2007Publication date: January 8, 2009Inventors: Hidenobu Nishikawa, Daido Komyoji, Hiroyuki Yamada, Yutaka Nakamura, Shuichi Takeda, Yasuharu Kikuchi
-
Patent number: 7471260Abstract: A semiconductor memory module formed of a mounted module (12) having a semiconductor memory device (16) and a control semiconductor device (18), a circuit board (14) which contains connection terminal (20) coupled with the control semiconductor device (18) and disposed so that it is exposed from the surface of outer case (42), and an antenna connection terminal electrode (22) disposed in the inside of outer case (42); and an antenna module (24) having a sheet board (26) which includes an antenna (28) disposed on one of the surfaces in the neighborhood of the edge along the sides, a layer (30) of magnetic substance disposed on the other surface, and an antenna terminal electrode (38) disposed on the one or the other surface. The antenna module (24) is overlaid on the mounted module (12), and the antenna connection terminal electrode (22) is connected with the antenna terminal electrode (38).Type: GrantFiled: February 2, 2006Date of Patent: December 30, 2008Assignee: Panasonic CorporationInventors: Shozo Ochi, Norihito Tsukahara, Kazuhiro Ikurumi, Hidenobu Nishikawa, Masato Hirano
-
Publication number: 20080150133Abstract: A semiconductor chip dual-sided assembly which has a higher degree of reliability of connections between semiconductor chips and a circuit substrate is realized. This is achieved by the assembly including a plurality of upper side pads (2a) provided on a substrate upper surface (1a); a plurality of lower side pads (2b) provided on a substrate lower surface (1b) corresponding to the upper side pads (2a) across the substrate (1), respectively; a first semiconductor chip (4) having first bumps (8a) joined to the upper side pads (2a), respectively; and a second semiconductor chip (5) having second bumps (8b) joined to the lower side pads (2b), respectively.Type: ApplicationFiled: December 28, 2005Publication date: June 26, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kojiro Nakamura, Hidenobu Nishikawa, Kentaro Kumazawa
-
Publication number: 20080111756Abstract: A semiconductor memory module formed of a mounted module (12) having a semiconductor memory device (16) and a control semiconductor device (18), a circuit board (14) which contains connection terminal (20) coupled with the control semiconductor device (18) and disposed so that it is exposed from the surface of outer case (42), and an antenna connection terminal electrode (22) disposed in the inside of outer case (42); and an antenna module (24) having a sheet board (26) which includes an antenna (28) disposed on one of the surfaces in the neighborhood of the edge along the sides, a layer (30) of magnetic substance disposed on the other surface, and an antenna terminal electrode (38) disposed on the one or the other surface. The antenna module (24) is overlaid on the mounted module (12), and the antenna connection terminal electrode (22) is connected with the antenna terminal electrode (38).Type: ApplicationFiled: February 2, 2006Publication date: May 15, 2008Inventors: Shozo Ochi, Norihito Tsukahara, Kazuhiro Ikurumi, Hidenobu Nishikawa, Masato Hirano
-
Patent number: 7355126Abstract: An electronic component and a circuit formation article are bonded together with a bonding material containing resin interposed therebetween. In a state that bumps of an electronic-component bonding region and electrodes of the circuit formation article are in mutual electrical contact, the electronic component and the circuit formation article are thermocompression-bonded to each other upon curing of the bonding material. A bonding-material flow regulating member of the electronic-component bonding region regulates flow of the bonding material toward a peripheral portion of the electronic-component bonding region during bonding of the circuit formation article to the electronic component.Type: GrantFiled: June 14, 2001Date of Patent: April 8, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hidenobu Nishikawa, Kazuto Nishida, Kazumichi Shimizu, Shuji Ono, Hiroyuki Otani
-
Publication number: 20070013067Abstract: A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip and the board is connected, the bumps are compressed, and the insulating resin is hardened.Type: ApplicationFiled: September 27, 2006Publication date: January 18, 2007Inventors: Kazuto Nishida, Hidenobu Nishikawa, Yoshinori Wada, Hiroyuki Otani
-
Patent number: 7076867Abstract: A pressurizing method for pressurizing a second component arranged on a first component, against the first component by using a pressurizing apparatus having a stage on which the first component is mounted, a tool, and a protection sheet supplying section. The tool is disposed so as to face the stage and moved between a first position at which the tool faces the first and second components while spaced therefrom, and a second position at which the tool is biased toward the stage to pressurize the second component against the first component. When the tool is at the second position, the protection sheet supplying section supplies a protection sheet so that the protection sheet is placed between the second component and the tool.Type: GrantFiled: December 24, 2002Date of Patent: July 18, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Akihiro Yamamoto, Sakae Kobayashi, Yoshikazu Yoshimura, Naoto Hosotani, Kenji Takahashi, Hiroshi Nasu, Naomi Kaino, Hidenobu Nishikawa
-
Patent number: 7060528Abstract: A semiconductor element mounting method is provided with high productivity. The method includes forming bumps on electrodes of a wafer in which a plurality of semiconductor elements have been formed, temporarily compression-bonding the wafer and an interposer via an insulative resin, curing the resin by performing heating and pressurization so that the wafer and the interposer are finally compression-bonded, wherein the electrodes of the wafer and electrodes of the interposer are bonded to each other, respectively, and wherein insulative resin overflowing from between the wafer and the interposer flows into grooves disposed so as to be coincident with dicing lines of the wafer, thus providing a uniform flow of the insulative resin, and thereafter, cutting and separating this bonded unit into individual semiconductor elements.Type: GrantFiled: September 25, 2002Date of Patent: June 13, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hidenobu Nishikawa, Kazuto Nishida, Kazumichi Shimizu, Hiroyuki Otani
-
Publication number: 20050224974Abstract: A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip and the board is connected, the bumps are compressed, and the insulating resin is hardened.Type: ApplicationFiled: June 13, 2005Publication date: October 13, 2005Inventors: Kazuto Nishida, Hidenobu Nishikawa, Yoshinori Wada, Hiroyuki Otani
-
Patent number: 6926796Abstract: A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip and the board is corrected, the bumps are compressed, and the insulating resin is hardened.Type: GrantFiled: January 26, 2000Date of Patent: August 9, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kazuto Nishida, Hidenobu Nishikawa, Yoshinori Wada, Hiroyuki Otani
-
Publication number: 20050155706Abstract: A chip is bonded on a circuit board by aligning in position bumps with board electrodes with interposition of an anisotropic conductive layer between the chip and the circuit board. The anisotropic conductive layer is a mixture of an insulating resin, conductive particles and an inorganic filler. The chip is pressed against the board with a pressure force of not smaller than 20 gf per bump by virtue of a tool, while warp of the chip and the board is connected, the bumps are compressed, and the insulating resin is hardened.Type: ApplicationFiled: February 23, 2005Publication date: July 21, 2005Inventors: Kazuto Nishida, Hidenobu Nishikawa, Yoshinori Wada, Hiroyuki Otani
-
Publication number: 20050036057Abstract: The present invention of a manufacturing method and a apparatus for manufacturing an image pickup device integrated with lens in which a lens holding part having an optical lens is automatically adjusted with respect to a package on which an imaging chip is mounted so that an optical image from an optical axis adjusting pattern is formed on the image plane of the imaging chip and the lens holding part and the package are fixed to each other with an adhesive used therebetween as a position adjusting member at the adjusted position, and an image pickup device integrated with lens thus manufactured having excellent properties.Type: ApplicationFiled: July 23, 2004Publication date: February 17, 2005Inventors: Kazuya Ushirokawa, Isamu Aokura, Koujirou Nakamura, Hidenobu Nishikawa, Tomonori Itoh
-
Patent number: 6770320Abstract: An apparatus and a method for applying a fluid, which enable an application amount of the fluid to be stabilized even at the start of fluid discharge and at the end of the fluid discharge. The apparatus includes an application head and a control unit, whereby operational control is carried out so that a discharge member is rotated and moved in a discharge direction along an axial direction of the discharge member when the fluid is to be discharged, while the rotation of the discharge member is stopped and the discharge member is moved in a direction opposite to the discharge direction when the discharge is to be stopped. The application amount of the fluid to be applied can be stabilized even at the start of fluid discharge and at the end of the fluid discharge.Type: GrantFiled: July 30, 2002Date of Patent: August 3, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Yamauchi, Hidenobu Nishikawa, Takashi Sonoda, Teruo Maruyama, Shuji Ono
-
Publication number: 20030166313Abstract: A semiconductor element mounting method is provided with high productivity. The method includes forming bumps on electrodes of a wafer in which a plurality of semiconductor elements have been formed, temporarily compression-bonding the wafer and an interposer via an insulative resin, curing the resin by heating and pressurization so that the wafer and the interposer are finally compression-bonded, where the electrodes of the wafer and electrodes of the interposer are bonded to each other, respectively, and where insulative resin overflowing from between the wafer and the interposer flows into grooves disposed so as to be coincident with dicing lines of the wafer, thus giving a uniform flow of the insulative resin, and thereafter, cutting and separating into individual semiconductor elements.Type: ApplicationFiled: September 25, 2002Publication date: September 4, 2003Inventors: Hidenobu Nishikawa, Kazuto Nishida, Kazumichi Shimizu, Hiroyuki Otani
-
Publication number: 20030145459Abstract: A pressurizing apparatus pressurizes a second component arranged on a first component against a first component. The pressurizing apparatus has a stage on which the first component is mounted, a tool, and a protection sheet supplying section. The tool is disposed so as to face the stage and moved between a first position at which the tool faces the first and second components with space and a second position at which the tool is biased toward the stage to pressurize the second component against the first component. When the tool is at the second position, the protection sheet supplying section supplies a protection sheet so that the protection sheet is placed between the second component and the tool.Type: ApplicationFiled: December 24, 2002Publication date: August 7, 2003Inventors: Akihiro Yamamoto, Sakae Kobayashi, Yoshikazu Yoshimura, Naoto Hosotani, Kenji Takahashi, Hiroshi Nasu, Naomi Kaino, Hidenobu Nishikawa
-
Publication number: 20030092326Abstract: An electronic component 1-1 and a circuit formation article 6-1 are bonded together with a bonding material 5 containing resin interposed therebetween. In a state that bumps 2 of an electronic-component bonding region 6a-1 and electrodes 7 of the circuit formation article are in mutual electrical contact, the electronic component and the circuit formation article are thermocompression-bonded to each other by a bonding-material flow regulating member 303 of the electronic-component bonding region under regulation of flow of the bonding material toward a peripheral portion, of the electronic-component bonding region, so that the bonding material is cured.Type: ApplicationFiled: December 16, 2002Publication date: May 15, 2003Inventors: Hidenobu Nishikawa, Kazuto Nishida, Kazumichi Shimizu, Shuji Ono, Hiroyuki Otani
-
Patent number: 6561408Abstract: There is provided an inclination prevention member for preventing a pressing part from inclining to a supporting part. Therefore a pressing face and a stage face can be arranged to be nearly parallel. The pressing face can be thus disposed with the higher parallelism to the bonding stage as compared with the conventional art, so that components and a circuit form object can be bonded with a high bonding quality.Type: GrantFiled: January 14, 2002Date of Patent: May 13, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Naoto Hosotani, Shuji Ono, Hidenobu Nishikawa, Mitsuo Maeno, Hiroshi Nasu