Abstract: A casing includes a support tubular part. An input shaft is rotatably supported in the casing. A motor is housed in the casing and rotationally drives the input shaft. An output shaft includes an output tubular part, which is formed in a tubular shape to rotatably couple an end part of a driven shaft in its inside and rotatably supported inside the support tubular part of the casing. The output shaft outputs the rotary force of the motor to the driven shaft with the transfer to the rotation of the input shaft. A bearing member is provided to be supported inside the support tubular part of the casing and rotatably bear the driven shaft in a state that the manual shaft is coupled to the output tubular part of the output shaft.

Abstract: A method for manufacturing a vertical trench IGBT includes: forming a body layer of a second conductivity type on a semiconductor substrate of a first conductivity type; forming a trench passing through the body layer; forming a trench gate in the trench via a gate insulating film; forming a polysilicon film containing an impurity of a first conductivity type on the body layer; diffusing the impurity from the polysilicon film into the body layer to form an emitter layer of a first conductivity type on the body layer; and forming a collector layer of a second conductivity type on a lower surface of the semiconductor substrate.

Abstract: A PIN diode has an n? drift layer, a p anode layer, an n buffer layer, an n+ layer, a front surface electrode and a back surface electrode. The n+ layer has an impurity concentration having a stepwise profile substantially fixed for a predetermined depth measured from a second major surface. The n buffer layer has an impurity concentration gently decreasing as seen at the n+ layer toward n? drift layer. The n? drift layer has an impurity concentration reflecting that of the semiconductor substrate and thus substantially fixed depthwise. The p anode layer has an impurity concentration relatively steeply decreasing as seen at a first major surface toward the n? drift layer. Thus there can be provided a semiconductor device that can provide characteristics, as desired, with high precision to accommodate the product applied, and a method of fabricating the semiconductor device.

Abstract: A semiconductor device includes: a substrate; a lower wiring on the substrate; an inter-layer insulating film covering the lower wiring; first and second upper wirings on the inter-layer insulating film and separated from each other; and a semi-insulating protective film covering the first and second upper wirings, wherein the protective film is not provided in a region right above the lower wiring and between the first upper wiring and the second upper wiring.

Abstract: A PIN diode has an n? drift layer, a p anode layer, an n buffer layer, an n+ layer, a front surface electrode and a back surface electrode. The n+ layer has an impurity concentration having a stepwise profile substantially fixed for a predetermined depth measured from a second major surface. The n buffer layer has an impurity concentration gently decreasing as seen at the n+ layer toward n? drift layer. The n? drift layer has an impurity concentration reflecting that of the semiconductor substrate and thus substantially fixed depthwise. The p anode layer has an impurity concentration relatively steeply decreasing as seen at a first major surface toward the n? drift layer. Thus there can be provided a semiconductor device that can provide characteristics, as desired, with high precision to accommodate the product applied, and a method of fabricating the semiconductor device.

Abstract: A semiconductor device includes a stepwise impurity layer provided at one of an anode portion and an cathode portion of the semiconductor device by introducing an impurity of a predetermined conduction type from a major surface of the semiconductor substrate through to a first depth to provide a first region of the semiconductor substrate having the impurity of the predetermined conduction type introduced therein. The predetermined conduction type is a same conduction type as a conduction type of the one of the anode portion and the cathode portion. The stepwise impurity layer is further provided by melting a second, predetermined region of the semiconductor substrate having a second depth deeper than the first depth and including the first region to make uniform the impurity of the predetermined conduction type in a concentration from the major surface through to the second depth to provide a uniform stepwise impurity concentration profile.

Abstract: A PIN diode has an n? drift layer, a p anode layer, an n buffer layer, an n+ layer, a front surface electrode and a back surface electrode. The n+ layer has an impurity concentration having a stepwise profile substantially fixed for a predetermined depth measured from a second major surface. The n buffer layer has an impurity concentration gently decreasing as seen at the n+ layer toward n? drift layer. The n? drift layer has an impurity concentration reflecting that of the semiconductor substrate and thus substantially fixed depthwise. The p anode layer has an impurity concentration relatively steeply decreasing as seen at a first major surface toward the n? drift layer. Thus there can be provided a semiconductor device that can provide characteristics, as desired, with high precision to accommodate the product applied, and a method of fabricating the semiconductor device.

Abstract: A PIN diode includes an anode electrode, a P layer, an I layer, an N layer and a cathode electrode. A polysilicon film is formed in a region near the pn junction or n+n junction where the density of carriers implanted in a forward bias state is relatively high, as a predetermined film having a crystal defect serving as a recombination center. The lifetime can thus be controlled precisely.

Abstract: A spool valve includes a sleeve, a spool and a filter. The sleeve is configured into a generally tubular form and has an opening, which communicates between inside and outside of the sleeve. The spool is axially slidably supported in the sleeve to change an opening degree of the opening of the sleeve. The filter is installed to the opening of the sleeve to filter fluid, which passes through the opening. The filter is configured into a generally rectangular form such that four outer edge portions of the filter are placed generally in a common imaginary plane. The sleeve includes two guide grooves that receive two opposed sides, respectively, of the filter.

Abstract: A manufacturing method of a semiconductor device having a semiconductor memory including a plurality of nonvolatile memory elements, comprising a step of forming a mask on the semiconductor memory and a step of irradiating through the mask with electron beams, the mask having transmission parts on one or more nonvolatile memory elements selected from the plurality of nonvolatile memory elements and a blocking part in which the electron beam is blocked, thereby said one or more nonvolatile memory elements are irradiated with electron beams without requiring an additional process.

Abstract: A zener diode, including: a semiconductor substrate; a first region of the first conductivity type formed on the surface of the semiconductor substrate; and a second region of the second conductivity type formed on the surface of the semiconductor substrate and included in the first region; and having a pn junction between the first and the second regions. The concentration of the impurity of the first conductivity type in the first region is highest near the surface of the semiconductor substrate, and the concentration of the impurity of the second conductivity type in the second region is highest near the surface of the semiconductor substrate.

Abstract: To provide a forged piston made of an aluminum alloy which is excellent in heat resistance and abrasion resistance and the lightening of which is enabled. A forged piston made of an aluminum alloy is provided including 8 to 18 wt % of Si, 0.5 to 3 wt % of Cu and 1 to 5 wt % of Ni, further including Al and unavoidable impurities, in which more Ni is included than Cu and the maximum length of an intermetallic compound generated by Al and Ni is 3 to 100 ?m.

Abstract: A manufacturing method of a semiconductor device having a semiconductor memory including a plurality of nonvolatile memory elements, comprising a step of forming a mask on the semiconductor memory and a step of irradiating through the mask with electron beams, the mask having transmission parts on one or more nonvolatile memory elements selected from the plurality of nonvolatile memory elements and a blocking part in which the electron beam is blocked, thereby said one or more nonvolatile memory elements are irradiated with electron beams without requiring an additional process.

Abstract: A semiconductor device in which a vertical pnp-bipolar transistor is formed in a prescribed element region on a semiconductor substrate includes: a buried n+-layer of a high concentration formed in the prescribed element region; and a p-type collector layer formed on the buried n+-layer. By introducing impurities that has a larger diffusion coefficient than the buried n+-layer, the collector layer can be formed on the buried n+-layer formed in common with other element regions, without any special masking.

Abstract: In an element formation region, a surface of an N− epitaxial layer is inclined upward from an end of a field oxide film to a sidewall of an opening. An external base diffusion layer at the surface of the N− epitaxial layer is inclined upward from a side of the field oxide film to the sidewall of the opening, and is exposed at the sidewall of the opening. A portion of the sidewall of the opening exposing the external base diffusion layer is tapered. The depth of a lower end of the external base diffusion layer or the sidewall of the opening is substantially equal to or smaller than that of a bottom of the opening. A decrease in breakdown voltage between an emitter and a base is suppressed, and decrease and variation of current gain hFE is suppressed.

Abstract: A first dopant impurity producing a conductivity type for formation of an intrinsic base diffusion layer and a dopant impurity producing the opposite conductivity type are implanted into a semiconductor substrate. An exposed surface of the semiconductor substrate is irradiated with a plasma, so that many crystalline defects are produced. Next, a polysilicon film is formed under conditions that cause the grain size to increase. In a portion of the polysilicon film located near the exposed surface of the semiconductor substrate, the grain size becomes relatively small, influenced by the crystalline defects in the substrate surface. In a portion of the polysilicon film located on the silicon oxide film, the grain size becomes relatively large, uninfluenced by the crystalline defects. Thus, degradation of electrical characteristics is suppressed, and variation in resistance of the resistance element is alleviated.

Abstract: In an element formation region, a surface of an N− epitaxial layer is inclined upward from an end of a field oxide film to a sidewall of an opening. An external base diffusion layer formed on the surface of the N− epitaxial layer is inclined upward from a side of the field oxide film to the sidewall of the opening, and is exposed at the sidewall of the opening. A portion of the sidewall of the opening exposing the external base diffusion layer is tapered. A depth of a lower end of the external base diffusion layer on the sidewall of the opening is substantially equal to or smaller than that of a bottom of the opening. With this, decrease in breakdown voltage between an emitter and a base is suppressed, and decrease and variation of a current gain hFE is suppressed.

Abstract: Impurity of a conductivity type for formation of an intrinsic base diffusion layer and impurity of the opposite conductivity type are implanted into a semiconductor substrate. An exposed surface of the semiconductor substrate is irradiated with plasma, so that many crystal defects are produced therein. Next, a polysilicon film is formed under the condition causing the grain size to increase. In a portion of the polysilicon film located near the exposed surface of the semiconductor substrate, the grain size becomes relatively small influenced by the crystal defects in the substrate surface. In a portion of the polysilicon film located on the silicon oxide film, the grain size becomes relatively large uninfluenced by the crystal defects. Thus, degradation of electric characteristics is suppressed, and variation in resistance value of the resistance element is alleviated.

Abstract: A semiconductor device in which a vertical pnp-bipolar transistor is formed in a prescribed element region on a semiconductor substrate includes: a buried n+-layer of a high concentration formed in the prescribed element region; and a p-type collector layer formed on the buried n+-layer. By introducing impurities that has a larger diffusion coefficient than the buried n+-layer, the collector layer can be formed on the buried n+-layer formed in common with other element regions, without any special masking.

Abstract: A bipolar transistor comprising an external base diffusion layer formed on the outer circumference of an intrinsic base diffusion layer is provided with the high withstand voltage and high reliability. A intrinsic base diffusion layer is formed on the substantially central portion of a semiconductor region surrounded by a separating insulation film on the major surface of a semiconductor substrate. An external base diffusion layer overlapping with the outer circumference of the intrinsic base diffusion layer, surrounding this intrinsic base diffusion layer, and reaching the separating insulation film is formed. Furthermore, common base diffusion layers overlapping with the intrinsic base diffusion layer, and overlapping with at least the inner circumference of the external base diffusion layer are formed. The depth of these common base diffusion layers is made deeper than the depth of the external base diffusion layer, but not exceeding the depth of the intrinsic base diffusion layer.