Patents by Inventor Hidenori Kamei

Hidenori Kamei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6841800
    Abstract: In the light-emitting gallium-nitride-group compound semiconductor devices using a substrate, the operating voltage is lowered and at the same time the occurrence of crack during crystal growth is suppressed, resulting in an improved manufacturing yield rate. The device includes a stacked structure of an n-type layer, a light-emitting layer and a p-type layer formed in the foregoing order on a substrate, and an n-side electrode formed on the surface of the n-type layer. The n-type layer is a laminate layer composed of, in the order from the substrate, first n-type layer and a second n-type layer having a carrier concentration higher than that of the first n-type layer. As the contact resistance between the n-type layer and the n-side electrode formed thereon is reduced, the operating voltage of a light-emitting device is lowered, and the power consumption decreased.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: January 11, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasunari Oku, Hidenori Kamei
  • Publication number: 20040104391
    Abstract: A chip-type light-emitting semiconductor device includes: a substrate 4; a blue LED 1 mounted on the substrate 4; and a luminescent layer 3 made of a mixture of yellow/yellowish phosphor particles 2 and a base material 13 (translucent resin). The yellow/yellowish phosphor particles 2 is a silicate phosphor which absorbs blue light emitted by the blue LED 1 to emit a fluorescence having a main emission peak in the wavelength range from 550 nm to 600 nm, inclusive, and which contains, as a main component, a compound expressed by the chemical formula: (Sr1−a1−b1−xBaa1Cab1Eux)2SiO4 (0≦a1≦0.3, 0≦b1≦0.8 and 0<x<1). The silicate phosphor particles disperse substantially evenly in the resin easily. As a result, excellent white light is obtained.
    Type: Application
    Filed: September 3, 2003
    Publication date: June 3, 2004
    Inventors: Toshihide Maeda, Shozo Oshio, Katsuaki Iwama, Hiromi Kitahara, Tadaaki Ikeda, Hidenori Kamei, Yasuyuki Hanada, Kei Sakanoue
  • Publication number: 20030132440
    Abstract: In the light-emitting gallium-nitride-group compound semiconductor devices using a substrate, the operating voltage is lowered and at the same time the occurrence of crack during crystal growth is suppressed, resulting in an improved manufacturing yield rate. The device includes a stacked structure of an n-type layer, a light-emitting layer and a p-type layer formed in the foregoing order on a substrate, and an n-side electrode formed on the surface of the n-type layer. The n-type layer is a laminate layer composed of, in the order from the substrate, first n-type layer and a second n-type layer having a carrier concentration higher than that of the first n-type layer. As the contact resistance between the n-type layer and the n-side electrode formed thereon is reduced, the operating voltage of a light-emitting device is lowered, and the power consumption decreased.
    Type: Application
    Filed: November 19, 2002
    Publication date: July 17, 2003
    Inventors: Yasunari Oku, Hidenori Kamei
  • Patent number: 6497944
    Abstract: In the light-emitting gallium-nitride-group compound semiconductor devices using an insulating substrate, the operating voltage is lowered and at the same time the occurrence of cracks during crystal growth is suppressed, resulting in an improved manufacturing yield rate. The device includes a stacked structure of an n-type layer, a light-emitting layer and a p-type layer formed in the foregoing order on an insulating substrate, and an n-side electrode formed on the surface of the n-type layer. The n-type layer is a laminate layer composed of, in the order from the substrate, a first n-type layer and a second n-type layer having a carrier concentration higher than that of the first n-type layer. As the contact resistance between the n-type layer and the n-side electrode formed thereon is reduced, the operating voltage of a light-emitting device is lowered, and the power consumption decreased.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: December 24, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasunari Oku, Hidenori Kamei
  • Patent number: 6445127
    Abstract: A gallium-nitride-group compound-semiconductor light-emitting device having an improved luminous intensity that makes it more suitable for use in the full-color outdoor display of an advanced performance. A gallium-nitride-group compound-semiconductor light-emitting device comprising an n-type layer 3, a light-emitting layer 4 and p-type layers 5, 6, the light-emitting layer 4 is doped with a p-type impurity, Mg for example, in a certain specific concentration, so a pn junction is formed within the light-emitting layer 4 and a light emission caused by the electron transition between conduction band and valence band is obtained. In a GaN group compound-semiconductor light-emitting device comprising at least an n-type clad layer 3, a p-type clad layer 5 and a light-emitting layer formed in between the clad layers 3, 5, stacked on a substrate 1.
    Type: Grant
    Filed: February 16, 1999
    Date of Patent: September 3, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasunari Oku, Hidenori Kamei
  • Patent number: 6365923
    Abstract: A nitride semiconductor light-emitting element containing an n-type layer, a light-emitting layer on the n-type layer, a first p-type layer on the light-emitting layer and a second p-type layer on the first p-type layer, the first p-type layer containing hydrogen element and a p-type impurity element, the second p-type layer containing hydrogen element and a p-type impurity element which is the same as or different from the p-type impurity element in the first p-type layer, and the ratio of hydrogen element to the p-type impurity element in the first p-type layer being lower than the ratio of hydrogen element to the p-type impurity element in the second p-type layer, can be produced by a process including the steps of (a) allowing the first p-type layer to grow by a metal organic chemical vapor deposition method in a reaction tube and (b) allowing the second p-type layer to grow by a metal organic chemical vapor deposition method in the reaction tube, the hydrogen content in the total mixture of gases fed int
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: April 2, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hidenori Kamei
  • Patent number: 6307219
    Abstract: An n-type clad layer, a light-emitting layer, a p-type clad layer of gallium-nitride-group compound semiconductor are stacked on a substrate in the order. The composition distribution of gallium-nitride-group compound semiconductor forming the p-type clad layer is varied in the direction of layer thickness at a substantially continuous change rate, or it is varied in change rate of the stepping mode, so as the forbidden band width gradually decreases along with an increasing distance from the light-emitting layer. With the above-described structure, the operating voltage is lowered, while the luminous efficiency is improved.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: October 23, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasunari Oku, Hidenori Kamei
  • Patent number: 6090211
    Abstract: A method and apparatus for forming a semiconductor thin layer on a substrate surface employs a gas outlet for supplying gas to the substrate, a rotatable holder for holding the substrate thereon such that a surface of the substrate is exposed to the gas while the substrate orbits with rotation of the holder, and a heater generates and supplies heat energy to the substrate. A cover wall extends over the surface of the substrate which is exposed to the gas. A distance between the exposed surface of the substrate and the cover wall in a direction parallel to a rotational axis of the rotatable holder decreases radially outward over the substrate orbiting with rotation of the holder about a rotational axis of the holder.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: July 18, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hidenori Kamei, Hidemi Takeishi, Yasunari Oku
  • Patent number: 6051847
    Abstract: In the present invention, by organometallic vapor deposition, a buffer layer containing indium is grown on a substrate and an n-type gallium nitride compound-based semiconductor thin film containing indium is grown on the buffer layer. Thus, the occurrence of distortion and crystal defects in the vicinity of the boundary surface between the buffer layer and the n-type gallium nitride compound-based semiconductor thin film is reduced, so that the gallium nitride compound-based semiconductor thin film having an excellent crystallinity can be obtained.As a gallium nitride compound-based semiconductor light emitting device using gallium nitride compound-based semiconductor thin films which has excellent light-emitting properties, there can be obtained a gallium nitride compound-based semiconductor light emitting device comprising a substrate, a buffer layer of Al.sub.1-x In.sub.x N (0<.times.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: April 18, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasunari Oku, Hidemi Takeishi, Hidenori Kamei, Shuuichi Shinagawa
  • Patent number: 5436924
    Abstract: Successively formed on an n-type InP substrate are an n-type InP first clad layer 1, an undoped GainAsP first light guide layer 11, an active layer 3 of the multiple quantum well structure arranged with the number of wells being 5 to 10 and the radiation wavelength being about 1.3 .mu.m, an undoped GainAsP second light guide layer 12, and a p-type InP clad layer 2, which are processed to constitute a mesa-type active region. The width of the active layer 3 is not less than 0.7 .mu.m and not more than 1.0 .mu.m, whereby the spectral width can be made not more than 2.5 nm in the temperature range of -45.degree. to +85.degree. C.
    Type: Grant
    Filed: August 5, 1994
    Date of Patent: July 25, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hidenori Kamei, Atsushi Miki
  • Patent number: 5093278
    Abstract: According to this invention, a first cladding layer of a first conductivity type, an active layer, a second cladding layer of a second conductivity type, and a cap layer much more susceptible to side etching than the second cladding layer susceptible to side etching than the second cladding layer are sequentially grown on a (100) crystal plane of a semiconductor substrate of the first conductivity type, and a stripe-like mask extending in a <011> direction is formed on the grown substrate with respect to each layer of the stacked substrate. This etching is performed in a crystal orientation for forming a reverse triangular mesa. However, since the cap layer is made of a material susceptible to side etching, a rounded mesa is formed. Thereafter, when a burying layer is formed on the etched portion by a vapor phase epitaxy method, the burying layer can be made to have a flat surface depending on crystal orientations.
    Type: Grant
    Filed: September 21, 1990
    Date of Patent: March 3, 1992
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Hidenori Kamei